{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,10]],"date-time":"2026-01-10T19:06:41Z","timestamp":1768072001430,"version":"3.49.0"},"reference-count":32,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2016,4,1]],"date-time":"2016-04-01T00:00:00Z","timestamp":1459468800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2016,4]]},"DOI":"10.1109\/jssc.2016.2520395","type":"journal-article","created":{"date-parts":[[2016,2,19]],"date-time":"2016-02-19T19:09:39Z","timestamp":1455908979000},"page":"881-892","source":"Crossref","is-referenced-by-count":25,"title":["A 3.8 mW\/Gbps Quad-Channel 8.5\u201313 Gbps Serial Link With a 5 Tap DFE and a 4 Tap Transmit FFE in 28 nm CMOS"],"prefix":"10.1109","volume":"51","member":"263","reference":[{"key":"ref32","first-page":"108","year":"0","journal-title":"IEEE Solid-State Circuits 2014 Technology Trends"},{"key":"ref31","first-page":"1","article-title":"A quad-channel 112-128 Gb\/s coherent transmitter in 40\ufffdnm CMOS","author":"garg","year":"0","journal-title":"Proc IEEE VLSI Circuits Symp"},{"key":"ref30","first-page":"160c","article-title":"A 288\ufffdfs RMS jitter versatile 8&#x2013;12.4\ufffdGHz wide-band fractional-N synthesizer for SONET and SerDes communication standards in 40\ufffdnm CMOS","author":"ahmadi","year":"0","journal-title":"Proc IEEE VLSI Circuits Symp"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2031021"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.884342"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2168871"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2185342"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2348556"},{"key":"ref15","first-page":"366","article-title":"A 78\ufffdmW 11.8 Gb\/s serial link transceiver with adaptive RX equalization and baud-rate CDR in 32\ufffdnm CMOS","author":"spagna","year":"0","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2031015"},{"key":"ref17","first-page":"1","article-title":"Wideband flexible-reach techniques for a 0.5&#x2013;16.3Gb\/s fully-adaptive transceiver in 20\ufffdnm CMOS","author":"savoj","year":"0","journal-title":"IEEE Custom Integrated Circuits Conf (CICC) Dig Tech Papers"},{"key":"ref18","first-page":"1","article-title":"Design of high-speed wireline transceivers for backplane communications in 28\ufffdnm CMOS","author":"savoj","year":"0","journal-title":"IEEE Custom Integrated Circuits Conf (CICC) Dig Tech Papers"},{"key":"ref19","first-page":"348c","article-title":"A 3.8\ufffdmW\/Gbps quad-channel 8.5&#x2013;13\ufffdGbps serial link with a 5-tap DFE and a 4-tap transmit FFE in 28\ufffdnm CMOS","author":"ali","year":"0","journal-title":"Proc IEEE VLSI Circuits Symp"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/4.845191"},{"key":"ref4","first-page":"276","article-title":"A 2.8\ufffdmW\/Gb\/s quad-channel 8.5&#x2013;11.4 Gb\/s quasi-digital transceiver in 28\ufffdnm CMOS","author":"nazemi","year":"0","journal-title":"Proc IEEE VLSI Circuits Symp"},{"key":"ref27","first-page":"435","article-title":"A 16 Gb\/s receiver with dc wander compensated rail-to-rail ac coupling and passive linear-equalizer in 22\ufffdnm CMOS","author":"francese","year":"0","journal-title":"Proc Eur Solid-State Circuits Conf"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.917522"},{"key":"ref6","first-page":"52","article-title":"A 12-Gb\/s transceiver in 32-nm bulk CMOS","author":"joshi","year":"0","journal-title":"Proc IEEE VLSI Circuits Symp"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2279419"},{"key":"ref5","first-page":"372","article-title":"A 5-25Gb\/s 1.6&#x2013;3.8\ufffdmW\/(Gb\/s) reconfigurable transceiver in 45\ufffdnm CMOS","author":"balamurugan","year":"0","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref8","first-page":"352c","article-title":"A 2.8\ufffdmW\/Gb\/s 14Gb\/s serial link transceiver in 65\ufffdnm CMOS","author":"saxena","year":"0","journal-title":"Proc IEEE VLSI Circuits Symp"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2412688"},{"key":"ref2","first-page":"152","article-title":"A quad 1-10Gb\/s serial transceiver in 90\ufffdnm CMOS","author":"bi","year":"0","journal-title":"Proc IEEE Asian Solid-State Circuits Conf"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2349992"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2075410"},{"key":"ref20","first-page":"97","article-title":"A 10\ufffdmW 3.6Gbps I\/O transmitter","author":"hatamkhani","year":"0","journal-title":"Proc IEEE VLSI Circuits Symp"},{"key":"ref22","first-page":"370","article-title":"A 32\ufffdmW 7.4 Gb\/s protocol-agile source-series terminated transmitter in 45\ufffdnm CMOS SOI","author":"dettloff","year":"0","journal-title":"IEEE Solid-State Ciruits Conf (ISSCC) Dig Tech Papers"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2010.5617598"},{"key":"ref24","first-page":"1","article-title":"A 19\ufffdmW\/lane SerDes transceiver for SFI-5.1 application","author":"fallahi","year":"0","journal-title":"IEEE Solid-State Ciruits Conf (ISSCC) Dig Tech Papers"},{"key":"ref23","first-page":"1","article-title":"A 10\ufffdGb\/s 10\ufffdmW 2-tap reconfigurable pre-emphasis transmitter in 65\ufffdnm LP CMOS","author":"lu","year":"0","journal-title":"IEEE Custom Integrated Circuits Conf (CICC) Dig Tech Papers"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2047473"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.908692"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/7446371\/7409940.pdf?arnumber=7409940","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:43:07Z","timestamp":1642005787000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7409940\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,4]]},"references-count":32,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2016.2520395","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2016,4]]}}}