{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,28]],"date-time":"2026-03-28T17:48:34Z","timestamp":1774720114189,"version":"3.50.1"},"reference-count":19,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"5","license":[{"start":{"date-parts":[[2016,5,1]],"date-time":"2016-05-01T00:00:00Z","timestamp":1462060800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"name":"Macao Science and Technology Development Fund (FDCT)","award":["053\/2014\/A1"],"award-info":[{"award-number":["053\/2014\/A1"]}]},{"name":"Research Grants of University of Macau","award":["MYRG2015-00088-AMSV"],"award-info":[{"award-number":["MYRG2015-00088-AMSV"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2016,5]]},"DOI":"10.1109\/jssc.2016.2522762","type":"journal-article","created":{"date-parts":[[2016,2,29]],"date-time":"2016-02-29T19:24:13Z","timestamp":1456773853000},"page":"1223-1234","source":"Crossref","is-referenced-by-count":36,"title":["An 11b 450 MS\/s Three-Way Time-Interleaved Subranging Pipelined-SAR ADC in 65 nm CMOS"],"prefix":"10.1109","volume":"51","author":[{"given":"Yan","family":"Zhu","sequence":"first","affiliation":[]},{"given":"Chi-Hang","family":"Chan","sequence":"additional","affiliation":[]},{"given":"Seng-Pan","family":"U","sequence":"additional","affiliation":[]},{"given":"Rui Paulo","family":"Martins","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","first-page":"1","article-title":"A 12b 160MS\/s synchronous two-step SAR ADC achieving 20.7fJ\/step FoM with opportunistic digital background calibration","author":"zhou","year":"0","journal-title":"IEEE Symp VLSI Circuits Dig Tech Papers"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2211695"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2012.6243804"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2014.6942059"},{"key":"ref14","first-page":"464","article-title":"An 11b 3.6GS\/s time-interleaved SAR ADC in 65\ufffdnm CMOS","author":"janssen","year":"0","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2015.2452331"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2264617"},{"key":"ref17","author":"gustavsson","year":"2000","journal-title":"CMOS Data Converters for Communications"},{"key":"ref18","doi-asserted-by":"crossref","first-page":"584","DOI":"10.1109\/TVLSI.2012.2190117","article-title":"10-bit 30-MS\/s SAR ADC using a switchback switching method","volume":"21","author":"huang","year":"2012","journal-title":"IEEE Trans Very Large Scale Integr Syst"},{"key":"ref19","first-page":"233","article-title":"A reconfigurable low-noise dynamic comparator with offset calibration in 90\ufffdnm CMOS","author":"chan","year":"0","journal-title":"IEEE Asian Solid-State Circuits Conf (A-SSCC)"},{"key":"ref4","first-page":"470","article-title":"An 8.6 ENOB 900MS\/s time-interleaved 2b\/cycle SAR ADC with a 1b\/cycle reconfiguration for resolution enhancement","author":"hong","year":"0","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ASSCC.2014.7008864"},{"key":"ref6","first-page":"386","article-title":"A 1.62GS\/s time-interleaved SAR ADC with digital background mismatch calibration achieving interleaving spurs below 70 dBFS","author":"dortz","year":"0","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref5","first-page":"86","article-title":"A 3.8\ufffdmW 8b 1GS\/s 2b\/cycle interleaving SAR ADC with compact DAC structure","author":"chan","year":"0","journal-title":"Proc IEEE Symp VLSI Circuits Dig Tech Papers"},{"key":"ref8","first-page":"1","article-title":"A 160 MS\/s, 11.1\ufffdmW, single-channel pipelined SAR ADC with 68.3\ufffddB SNDR","author":"tripathi","year":"0","journal-title":"Proc IEEE Custom Integrated Circuits Conf"},{"key":"ref7","first-page":"384","article-title":"A 1GS\/s 10b 18.9\ufffdmW time-interleaved SAR ADC with background timing-skew calibration","author":"lee","year":"0","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2048498"},{"key":"ref1","first-page":"386","article-title":"A 10b 100-MS\/s 1.13\ufffdmW SAR ADC with binary-scaled error compensation","author":"liu","year":"0","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref9","first-page":"1","article-title":"A 12-bit 210-MS\/s 5.3-mW pipelined-SAR ADC with a passive residue transfer technique","author":"lin","year":"0","journal-title":"IEEE Symp VLSI Circuits Dig Tech Papers"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/7465846\/07421953.pdf?arnumber=7421953","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:43:23Z","timestamp":1642005803000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7421953\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,5]]},"references-count":19,"journal-issue":{"issue":"5"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2016.2522762","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2016,5]]}}}