{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,19]],"date-time":"2026-02-19T16:07:35Z","timestamp":1771517255534,"version":"3.50.1"},"reference-count":38,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"6","license":[{"start":{"date-parts":[[2016,6,1]],"date-time":"2016-06-01T00:00:00Z","timestamp":1464739200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/OAPA.html"}],"funder":[{"name":"MIC, SCOPE, STARC, STAR, and VDEC in collaboration with Synopsys, Inc."}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2016,6]]},"DOI":"10.1109\/jssc.2016.2546304","type":"journal-article","created":{"date-parts":[[2016,5,6]],"date-time":"2016-05-06T15:20:08Z","timestamp":1462548008000},"page":"1385-1397","source":"Crossref","is-referenced-by-count":59,"title":["A 2.2 GHz -242 dB-FOM 4.2 mW ADC-PLL Using Digital Sub-Sampling Architecture"],"prefix":"10.1109","volume":"51","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-1658-9596","authenticated-orcid":false,"given":"Teerachot","family":"Siriburanon","sequence":"first","affiliation":[]},{"given":"Satoshi","family":"Kondo","sequence":"additional","affiliation":[]},{"given":"Kento","family":"Kimura","sequence":"additional","affiliation":[]},{"given":"Tomohiro","family":"Ueno","sequence":"additional","affiliation":[]},{"given":"Satoshi","family":"Kawashima","sequence":"additional","affiliation":[]},{"given":"Tohru","family":"Kaneko","sequence":"additional","affiliation":[]},{"given":"Wei","family":"Deng","sequence":"additional","affiliation":[]},{"given":"Masaya","family":"Miyahara","sequence":"additional","affiliation":[]},{"given":"Kenichi","family":"Okada","sequence":"additional","affiliation":[]},{"given":"Akira","family":"Matsuzawa","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref38","doi-asserted-by":"crossref","first-page":"117","DOI":"10.1109\/TCSII.2008.2010189","article-title":"Jitter analysis and a benchmarking figure-of-merit for phase-locked loops","volume":"56","author":"gao","year":"2009","journal-title":"IEEE Trans Circuits Syst II"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2004867"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2230542"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2003.813584"},{"key":"ref30","first-page":"388","article-title":"A 2.2\ufffdGb\/s 7b 27.4\ufffdmW time-based folding-flash ADC with resistively averaged voltage-to-time amplifiers","author":"miyahara","year":"0","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2015.7231354"},{"key":"ref36","first-page":"94","article-title":"Bang-bang digital PLLs at 11 and 20\ufffdGHz with sub-200\ufffdfs integrated jitter for high-speed serial communication applications","author":"rylakov","year":"0","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref35","first-page":"407","article-title":"A high-swing complementary class-C VCO","author":"farnori","year":"0","journal-title":"Proc IEEE Eur Solid-State Circuits Conf (ESSCIRC)"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2227603"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2028753"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2005704"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2230543"},{"key":"ref13","first-page":"350","article-title":"A 40\ufffdnm dual-band 3-stream 802.11a\/b\/g\/n\/ac MIMO WLAN SoC with 1.1\ufffdGb\/s over-the-air throughput","author":"he","year":"0","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2385753"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2013.2273732"},{"key":"ref16","first-page":"192","article-title":"An 8.5\ufffdmW, $0.07\\; \\text{mm}^{2}$ ADPLL in 28\ufffdnm CMOS with sub-ps resolution TDC and < 230\ufffdfs RMS jitter","author":"shen","year":"0","journal-title":"IEEE Symp VLSI Circuits (VLSIC) Dig"},{"key":"ref17","first-page":"440","article-title":"A 2.2\ufffdGHz&#x2013;242\ufffddB-FOM 4.2\ufffdmW ADC-PLL using digital sub-sampling architecture","author":"siriburanon","year":"0","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2403373"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2359670"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2053094"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/RFIC.2014.6851670"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/4.760369"},{"key":"ref3","first-page":"366","article-title":"A 42\ufffdmW 230\ufffdfs-jitter sub-sampling 60\ufffdGHz PLL in 40\ufffdnm CMOS","author":"szortyka","year":"0","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.857417"},{"key":"ref29","first-page":"394","article-title":"A 2.5\ufffdV, 30\ufffdMHz-100Mhz, 7th-order, equiripple group-delay continuous-time filter and variable-gain amplifier implemented in $0.25 \\;\\mu\\text{m}$ CMOS","author":"gopinathan","year":"0","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2011.2150890"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2259031"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2011.2163981"},{"key":"ref2","first-page":"2635","article-title":"A low noise sub-sampling PLL in which divider noise is eliminated and PD\/CP noise is not multiplied by ${N^2}$","volume":"46","author":"gao","year":"2009","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2076591"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.835833"},{"key":"ref20","first-page":"268","article-title":"A sub-sampling all-digital fractional-N frequency synthesizer with $-111\\; \\text{dBc\/Hz}$ in-band phase noise and an FOM of $-242\\;\\text{dB}$","author":"chen","year":"0","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2047435"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1002\/0470041951"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2014709"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2014.2304656"},{"key":"ref26","first-page":"194","article-title":"A 12\ufffdGHz 210\ufffdfs 6\ufffdmW digital PLL with sub-sampling binary phase detector and voltage-time modulated DCO","author":"ru","year":"0","journal-title":"IEEE Symp VLSI Circuits (VLSIC) Dig"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.876206"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/ieeexplore.ieee.org\/iel7\/4\/7490327\/07463453.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/7490327\/07463453.pdf?arnumber=7463453","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:26:21Z","timestamp":1642004781000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7463453\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,6]]},"references-count":38,"journal-issue":{"issue":"6"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2016.2546304","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2016,6]]}}}