{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,10]],"date-time":"2026-01-10T18:48:51Z","timestamp":1768070931961,"version":"3.49.0"},"reference-count":14,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"8","license":[{"start":{"date-parts":[[2016,8,1]],"date-time":"2016-08-01T00:00:00Z","timestamp":1470009600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2016,8]]},"DOI":"10.1109\/jssc.2016.2550499","type":"journal-article","created":{"date-parts":[[2016,5,6]],"date-time":"2016-05-06T15:20:08Z","timestamp":1462548008000},"page":"1744-1755","source":"Crossref","is-referenced-by-count":10,"title":["A 1.8\u00a0pJ\/bit &lt;inline-formula&gt; &lt;tex-math notation=\"LaTeX\"&gt;$16 \\times 16\\;\\text{Gb\/s}$&lt;\/tex-math&gt; &lt;\/inline-formula&gt; Source-Synchronous Parallel Interface in 32\u00a0nm SOI CMOS with Receiver Redundancy for Link Recalibration"],"prefix":"10.1109","volume":"51","author":[{"given":"Timothy O.","family":"Dickson","sequence":"first","affiliation":[]},{"given":"Yong","family":"Liu","sequence":"additional","affiliation":[]},{"given":"Ankur","family":"Agrawal","sequence":"additional","affiliation":[]},{"given":"John F.","family":"Bulzacchelli","sequence":"additional","affiliation":[]},{"given":"Herschel A.","family":"Ainspan","sequence":"additional","affiliation":[]},{"given":"Zeynep","family":"Toprak-Deniz","sequence":"additional","affiliation":[]},{"given":"Benjamin D.","family":"Parker","sequence":"additional","affiliation":[]},{"given":"Michael P.","family":"Beakes","sequence":"additional","affiliation":[]},{"given":"Mounir","family":"Meghelli","sequence":"additional","affiliation":[]},{"given":"Daniel J.","family":"Friedman","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","author":"razavi","year":"2012","journal-title":"Design of Integrated Circuits for Optical Communications"},{"key":"ref11","first-page":"126","article-title":"A 16\ufffdGb\/s\/link, 64\ufffdGB\/s bidirectional link asymmetric memory interface cell","author":"chang","year":"0","journal-title":"Symp VLSI Circuits Dig"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2185370"},{"key":"ref13","first-page":"138","article-title":"A 4.1\ufffdpJ\/b 16\ufffdGb\/s coded differential bidirectional parallel electrical link","author":"amirkhany","year":"0","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref14","first-page":"402","article-title":"A scalable 0.128-to-1Tb\/s 0.8-to-2.6pJ\/b 64-lane parallel I\/O in 32\ufffdnm CMOS","author":"mansuri","year":"0","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref4","first-page":"198","article-title":"A 28\ufffdGHz hybrid PLL in 32\ufffdnm SOI CMOS","author":"ferriss","year":"0","journal-title":"Symp VLSI Circuits Dig"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2412688"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2216414"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2216412"},{"key":"ref8","first-page":"186","article-title":"Continuous-time linear equalization with programmable active-peaking transistor arrays in a 14\ufffdnm FinFET 2\ufffdmW\/Gb\/s 16\ufffdGb\/s 2-tap speculative DFE receiver","author":"francese","year":"0","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref7","first-page":"158","article-title":"A 3\ufffdGHz, 32\ufffddB CMOS limiting amplifier for SONET OC-48 receivers","author":"sackinger","year":"0","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref2","article-title":"A 1.8\ufffdpJ\/bit 16&#x00D7;16-Gb\/s source synchronous parallel interface in 32\ufffdnm SOI CMOS with receiver redundancy for link recalibration","author":"dickson","year":"0","journal-title":"Proc IEEE Custom Integrated Circuits Conf (CICC)"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2185184"},{"key":"ref9","first-page":"60","article-title":"A 16-to-40\ufffdGb\/s quarter-rate NRZ\/PAM4 dual-mode transmitter in 14\ufffdnm CMOS","author":"kim","year":"0","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/7526339\/07463472.pdf?arnumber=7463472","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:02:47Z","timestamp":1642003367000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7463472\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,8]]},"references-count":14,"journal-issue":{"issue":"8"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2016.2550499","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2016,8]]}}}