{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,1,18]],"date-time":"2024-01-18T08:34:03Z","timestamp":1705566843918},"reference-count":44,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"6","license":[{"start":{"date-parts":[[2016,6,1]],"date-time":"2016-06-01T00:00:00Z","timestamp":1464739200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2016,6]]},"DOI":"10.1109\/jssc.2016.2557810","type":"journal-article","created":{"date-parts":[[2016,5,30]],"date-time":"2016-05-30T18:05:49Z","timestamp":1464631549000},"page":"1361-1373","source":"Crossref","is-referenced-by-count":2,"title":["A Fractional-N Counter-Assisted DPLL With Parallel Sampling ILFD"],"prefix":"10.1109","volume":"51","author":[{"given":"Supeng","family":"Liu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yuanjin","family":"Zheng","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/TMTT.2003.818579"},{"key":"ref38","first-page":"391","article-title":"A transfer-curve-folded DCO in $0.13~\\mu $ m CMOS","author":"zhan","year":"2008","journal-title":"IEEE RFIC Symp Dig"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.809519"},{"key":"ref32","article-title":"Delay-locked loops&#x2014;An overview","author":"yang","year":"2003","journal-title":"Phase Locking in High Performance Systems"},{"key":"ref31","doi-asserted-by":"crossref","first-page":"1773","DOI":"10.1109\/JSSC.2014.2312412","article-title":"A 9.2 GHz digital phase-locked loop with peaking-free transfer function","volume":"49","author":"sigang","year":"2014","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2012363"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2011.2163981"},{"key":"ref36","doi-asserted-by":"crossref","first-page":"1081","DOI":"10.1109\/JSSC.2014.2301764","article-title":"A 56.4-to-63.4 GHz multi-rate all-digital fractional-N PLL for FMCW radar applications in 65 nm CMOS","volume":"49","author":"wanghua","year":"2014","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2006.886896"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/TMTT.2012.2183379"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/4.823449"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/ASSCC.2007.4425723"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2040306"},{"key":"ref12","first-page":"143","article-title":"A 9.2&#x2013;12GHz, 90nm digital fractional-N synthesizer with stochastic TDC calibration and -35\/-41dBc integrated phase noise in the 5\/2.5GHz bands","author":"ravi","year":"2010","journal-title":"Proc IEEE Symp VLSI Circuits"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2063630"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2076591"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2008.4585972"},{"key":"ref16","first-page":"188","article-title":"A 320fs-RMS-jitter and 300kHz-BW all-digital fractional-N PLL with self-corrected TDC and fast temperature tacking loop for WiMax\/WLAN 11n","author":"chang","year":"2009","journal-title":"VLSI Symp Dig"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2014709"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2074950"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2010.5433839"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2185190"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2314436"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.811975"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2361351"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2259031"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2012.2188474"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2077370"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/RFIC.2005.1489847"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2005704"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2104270"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2005.858754"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2162769"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2015.2447001"},{"key":"ref22","first-page":"172","article-title":"An 860W 2.1-to-2.7GHz all-digital PLL-based frequency modulator with a DTC-assisted snapshot TDC for WPAN (Bluetooth Smart and ZigBee) applications","author":"chillara","year":"0","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2403373"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/LMWC.2015.2409792"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.857417"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/TMTT.2008.916868"},{"key":"ref23","first-page":"54","article-title":"A 5.3 GHz digital-to-time-converter-based fractional-N all-digital PLL","author":"pavlovic","year":"2011","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/4.845191"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TMTT.2013.2244224"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2009.5118475"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.903058"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/7490327\/07480772.pdf?arnumber=7480772","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:11:27Z","timestamp":1642003887000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7480772\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,6]]},"references-count":44,"journal-issue":{"issue":"6"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2016.2557810","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2016,6]]}}}