{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,26]],"date-time":"2026-02-26T15:48:20Z","timestamp":1772120900336,"version":"3.50.1"},"reference-count":26,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"3","license":[{"start":{"date-parts":[[2017,3,1]],"date-time":"2017-03-01T00:00:00Z","timestamp":1488326400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["61474001"],"award-info":[{"award-number":["61474001"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["61574001"],"award-info":[{"award-number":["61574001"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Natural Science Fund for Colleges and Universities in Anhui Province","award":["KJ2013A006"],"award-info":[{"award-number":["KJ2013A006"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2017,3]]},"DOI":"10.1109\/jssc.2016.2634701","type":"journal-article","created":{"date-parts":[[2016,12,26]],"date-time":"2016-12-26T19:25:38Z","timestamp":1482780338000},"page":"669-677","source":"Crossref","is-referenced-by-count":21,"title":["A Pipeline Replica Bitline Technique for Suppressing Timing Variation of SRAM Sense Amplifiers in a 28-nm CMOS Process"],"prefix":"10.1109","volume":"52","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-3314-1606","authenticated-orcid":false,"given":"Zhiting","family":"Lin","sequence":"first","affiliation":[]},{"given":"Xiulong","family":"Wu","sequence":"additional","affiliation":[]},{"given":"Zhi","family":"Li","sequence":"additional","affiliation":[]},{"given":"Lijun","family":"Guan","sequence":"additional","affiliation":[]},{"given":"Chunyu","family":"Peng","sequence":"additional","affiliation":[]},{"given":"Changyong","family":"Liu","sequence":"additional","affiliation":[]},{"given":"Junning","family":"Chen","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/4.705359"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/AMS.2011.58"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2008.4672108"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.917568"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2185180"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ASQED.2013.6643593"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1049\/el.2015.0574"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2012.6243809"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2008.2010101"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2164294"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2273835"},{"key":"ref3","first-page":"236","article-title":"A 7ns-access-time 25 $\\mu $ W\/MHz 128kb SRAM for low-power fast wake-up MCU in 65nm CMOS with 27fA\/b retention current","author":"fukuda","year":"2014","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1587\/elex.12.20150102"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2014.02.015"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2011.2165389"},{"key":"ref7","doi-asserted-by":"crossref","first-page":"264","DOI":"10.1109\/TCSII.2014.2304893","article-title":"A multiple-stage parallel replica-bitline delay addition technique for reducing timing variation of SRAM sense amplifiers","volume":"61","author":"wu","year":"2014","journal-title":"IEEE Trans Circuits Syst II Express Briefs"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TCSVT.2011.2105550"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2009.5280731"},{"key":"ref1","first-page":"314","article-title":"A 28nm 256Kb 6T-SRAM with 280mV improvement in VMIN using a dual-split-control assist scheme","author":"chang","year":"2015","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1587\/elex.11.20130992"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1587\/elex.13.20150951"},{"key":"ref21","first-page":"28","article-title":"A 4T dual replica-bitline delay technique for process-variation-tolerant low voltage SRAM sense amplifier timing","volume":"32","author":"ye","year":"2015","journal-title":"Microelectron Comput"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2015.2469596"},{"key":"ref23","doi-asserted-by":"crossref","first-page":"700","DOI":"10.1631\/FITEE.1400439","article-title":"Multi-stage dual replica bit-line delay technique for process-variation-robust timing of low voltage SRAM sense amplifier","volume":"16","author":"tan","year":"2015","journal-title":"Frontiers Inf Technol Electron Eng"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1989.572629"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2011042"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/7865876\/07797555.pdf?arnumber=7797555","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:19:56Z","timestamp":1642004396000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7797555\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,3]]},"references-count":26,"journal-issue":{"issue":"3"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2016.2634701","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2017,3]]}}}