{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,2]],"date-time":"2026-04-02T09:13:58Z","timestamp":1775121238261,"version":"3.50.1"},"reference-count":20,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2017,4,1]],"date-time":"2017-04-01T00:00:00Z","timestamp":1491004800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2017,4]]},"DOI":"10.1109\/jssc.2017.2647925","type":"journal-article","created":{"date-parts":[[2017,2,22]],"date-time":"2017-02-22T19:13:09Z","timestamp":1487790789000},"page":"1134-1143","source":"Crossref","is-referenced-by-count":6,"title":["DPLL for Phase Noise Cancellation in Ring Oscillator-Based Quadrature Receivers"],"prefix":"10.1109","volume":"52","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-1948-305X","authenticated-orcid":false,"given":"Zuow-Zun","family":"Chen","sequence":"first","affiliation":[]},{"given":"Yen-Cheng","family":"Kuan","sequence":"additional","affiliation":[]},{"given":"Yilei","family":"Li","sequence":"additional","affiliation":[]},{"given":"Boyu","family":"Hu","sequence":"additional","affiliation":[]},{"given":"Chien-Heng","family":"Wong","sequence":"additional","affiliation":[]},{"given":"Mau-Chung Frank","family":"Chang","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2005704"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2162912"},{"key":"ref12","first-page":"190","article-title":"A digital PLL with feedforward multitone spur cancellation loop achieving <-73dBc fractional spur and <-110dBc reference spur in 65nm CMOS","author":"ho","year":"2016","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2006.886202"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2217854"},{"key":"ref15","first-page":"270","article-title":"A 2.4GHz ADPLL with digital-regulated supply-noise-insensitive and temperature-self-compensated ring DCO","author":"huang","year":"2014","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref16","first-page":"1","article-title":"Tutorial on digital phase-locked loops","author":"perrott","year":"2009","journal-title":"Proc IEEE CICC"},{"key":"ref17","first-page":"268","article-title":"A sub-sampling all-digital fractional-N frequency synthesizer with ?111dBc\/Hz in-band phase noise and an FOM of ?242dB","author":"chen","year":"2015","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref18","doi-asserted-by":"crossref","first-page":"117","DOI":"10.1109\/TCSII.2008.2010189","article-title":"Jitter analysis and a benchmarking figure-of-merit for phase-locked loops","volume":"56","author":"gao","year":"2009","journal-title":"IEEE Trans Circuits Syst II Express Briefs"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.903060"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2252515"},{"key":"ref3","doi-asserted-by":"crossref","first-page":"626","DOI":"10.1109\/JSSC.2015.2511157","article-title":"A 2.4 GHz 4 mW integer-N inductorless RF synthesizer","volume":"51","author":"kong","year":"2016","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.831598"},{"key":"ref5","first-page":"114","article-title":"Digital PLL for phase noise cancellation in ring oscillator-based I\/Q receivers","author":"chen","year":"2016","journal-title":"Symp VLSI Circuits Dig"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/RFIC.2014.6851668"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2011.2163981"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2458956"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2283758"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2006.886896"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2075210"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/7888613\/07862146.pdf?arnumber=7862146","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:26:40Z","timestamp":1642004800000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7862146\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,4]]},"references-count":20,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2017.2647925","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2017,4]]}}}