{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,5]],"date-time":"2026-02-05T06:35:34Z","timestamp":1770273334076,"version":"3.49.0"},"reference-count":30,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"9","license":[{"start":{"date-parts":[[2017,9,1]],"date-time":"2017-09-01T00:00:00Z","timestamp":1504224000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2017,9,1]],"date-time":"2017-09-01T00:00:00Z","timestamp":1504224000000},"content-version":"am","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2017,9,1]],"date-time":"2017-09-01T00:00:00Z","timestamp":1504224000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2017,9,1]],"date-time":"2017-09-01T00:00:00Z","timestamp":1504224000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100000001","name":"NSF under CAREER","doi-asserted-by":"publisher","award":["EECS-0954969"],"award-info":[{"award-number":["EECS-0954969"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100002418","name":"Intel","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100002418","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2017,9]]},"DOI":"10.1109\/jssc.2017.2718670","type":"journal-article","created":{"date-parts":[[2017,8,1]],"date-time":"2017-08-01T18:33:29Z","timestamp":1501612409000},"page":"2306-2320","source":"Crossref","is-referenced-by-count":11,"title":["A 5GHz Digital Fractional- $N$ PLL Using a 1-bit Delta\u2013Sigma Frequency-to-Digital Converter in 65 nm CMOS"],"prefix":"10.1109","volume":"52","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-2559-6915","authenticated-orcid":false,"given":"Mrunmay","family":"Talegaonkar","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1737-7950","authenticated-orcid":false,"given":"Tejasvi","family":"Anand","sequence":"additional","affiliation":[]},{"given":"Ahmed","family":"Elkholy","sequence":"additional","affiliation":[]},{"given":"Amr","family":"Elshazly","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0339-5792","authenticated-orcid":false,"given":"Romesh Kumar","family":"Nandwana","sequence":"additional","affiliation":[]},{"given":"Saurabh","family":"Saxena","sequence":"additional","affiliation":[]},{"given":"Brian","family":"Young","sequence":"additional","affiliation":[]},{"given":"Woo-Seok","family":"Choi","sequence":"additional","affiliation":[]},{"given":"Pavan Kumar","family":"Hanumolu","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref30","first-page":"317","article-title":"A 5.8GHz digital arbitrary phase-setting type II PLL in 65nm CMOS with 2.25° resolution","author":"li","year":"2012","journal-title":"Proc IEEE Asian Solid-State Circuits Conf (A-SSCC)"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2468712"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.1993.393928"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/82.275664"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/4.553171"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TMTT.2011.2114897"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2005435"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2012.2220502"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.820858"},{"key":"ref18","first-page":"1","article-title":"A 4.4-5.4GHz digital fractional-N PLL using \n$\\Delta \\!\\Sigma $\n frequency-to-digital converter","author":"talegaonkar","year":"2014","journal-title":"Proc Symp VLSI Circuits (VLSIC)"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2002.800925"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2197130"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2272340"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2104270"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2162917"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.857417"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2582854"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2385753"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/4.938372"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2077370"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2230543"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2361523"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2005704"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2217856"},{"key":"ref22","first-page":"416","article-title":"A wideband fractional-N ring PLL with fractional-spur suppression using spectrally shaped segmentation","author":"kao","year":"2013","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2254552"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.884342"},{"key":"ref23","first-page":"314","article-title":"A double-tail latch-type voltage sense amplifier with 18ps setup+hold time","author":"schinkel","year":"2007","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2028753"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2385756"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/ieeexplore.ieee.org\/ielaam\/4\/8015205\/7999180-aam.pdf","content-type":"application\/pdf","content-version":"am","intended-application":"syndication"},{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/8015205\/07999180.pdf?arnumber=7999180","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,4,8]],"date-time":"2022-04-08T18:55:49Z","timestamp":1649444149000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7999180\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,9]]},"references-count":30,"journal-issue":{"issue":"9"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2017.2718670","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2017,9]]}}}