{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,13]],"date-time":"2026-03-13T14:58:10Z","timestamp":1773413890262,"version":"3.50.1"},"reference-count":28,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"2","license":[{"start":{"date-parts":[[2018,2,1]],"date-time":"2018-02-01T00:00:00Z","timestamp":1517443200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2018,2]]},"DOI":"10.1109\/jssc.2017.2757005","type":"journal-article","created":{"date-parts":[[2017,11,13]],"date-time":"2017-11-13T19:14:27Z","timestamp":1510600467000},"page":"431-444","source":"Crossref","is-referenced-by-count":6,"title":["CHIMERA: A Field-Programmable Mixed-Signal IC With Time-Domain Configurable Analog Blocks"],"prefix":"10.1109","volume":"53","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-6445-5202","authenticated-orcid":false,"given":"Yunju","family":"Choi","sequence":"first","affiliation":[]},{"given":"Yoontaek","family":"Lee","sequence":"additional","affiliation":[]},{"given":"Seung-Heon","family":"Baek","sequence":"additional","affiliation":[]},{"given":"Sung-Joon","family":"Lee","sequence":"additional","affiliation":[]},{"given":"Jaeha","family":"Kim","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","first-page":"138","article-title":"A field-programmable mixed-signal IC with time-domain configurable analog blocks","author":"choi","year":"2016","journal-title":"Proc IEEE Symp VLSI Circuits"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2006.33"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.917500"},{"key":"ref13","first-page":"3934","article-title":"A time-based analog-to-digital converter using a multi-phase voltage controlled oscillator","author":"kim","year":"2006","journal-title":"Proc IEEE Int Symp Circuits Syst"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TIA.2015.2411656"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TIA.2016.2541079"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2007.4342700"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2312412"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-5145-4"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/4.309912"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2015.2435691"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2002.808298"},{"key":"ref27","author":"murmann","year":"2017","journal-title":"ADC Performance Survey 1997–2013"},{"key":"ref3","first-page":"70","article-title":"A continuous-time hexagonal field-programmable analog array in 0.13 $\\mu$ m CMOS with 186 MHz GBW","author":"becker","year":"2008","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2012.2211049"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2056832"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2015.2512718"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2164295"},{"key":"ref2","first-page":"233","article-title":"A user programmable reconfigurable gate array","author":"carter","year":"1986","journal-title":"Proc Custom Integr Circuits Conf"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2015.2442752"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2015.2392104"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/92.365457"},{"key":"ref22","year":"2017","journal-title":"ABC A System for Sequential Synthesis and Verification"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2010.31"},{"key":"ref24","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4614-3594-5","author":"farooq","year":"2012","journal-title":"Tree-Based Heterogeneous FPGA Architectures Application Specific Exploration and Optimization"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/1508128.1508150"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2006.889443"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1016\/0029-554X(80)90128-7"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/8271882\/08106657.pdf?arnumber=8106657","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,8,28]],"date-time":"2023-08-28T12:36:52Z","timestamp":1693226212000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/8106657\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,2]]},"references-count":28,"journal-issue":{"issue":"2"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2017.2757005","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2018,2]]}}}