{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,19]],"date-time":"2026-06-19T16:07:19Z","timestamp":1781885239244,"version":"3.54.5"},"reference-count":27,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"3","license":[{"start":{"date-parts":[[2018,3,1]],"date-time":"2018-03-01T00:00:00Z","timestamp":1519862400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2018,3,1]],"date-time":"2018-03-01T00:00:00Z","timestamp":1519862400000},"content-version":"am","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2018,3,1]],"date-time":"2018-03-01T00:00:00Z","timestamp":1519862400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2018,3,1]],"date-time":"2018-03-01T00:00:00Z","timestamp":1519862400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100000001","name":"National Science Foundation (NSF)","doi-asserted-by":"publisher","award":["1254459"],"award-info":[{"award-number":["1254459"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000001","name":"National Science Foundation (NSF)","doi-asserted-by":"publisher","award":["1509767"],"award-info":[{"award-number":["1509767"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000001","name":"National Science Foundation (NSF)","doi-asserted-by":"publisher","award":["1527320"],"award-info":[{"award-number":["1527320"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2018,3]]},"DOI":"10.1109\/jssc.2017.2768404","type":"journal-article","created":{"date-parts":[[2017,12,7]],"date-time":"2017-12-07T19:32:30Z","timestamp":1512675150000},"page":"789-798","source":"Crossref","is-referenced-by-count":22,"title":["A 6-bit 0.81-mW 700-MS\/s SAR ADC With Sparkle-Code Correction, Resolution Enhancement, and Background Window Width Calibration"],"prefix":"10.1109","volume":"53","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-2802-0444","authenticated-orcid":false,"given":"Yeonam","family":"Yoon","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Nan","family":"Sun","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref10","first-page":"417","article-title":"A 1.4 mW 8b 350 MS\/s loop-unrolled SAR ADC with background offset calibration in 40 nm CMOS","author":"ragab","year":"2016","journal-title":"Proc IEEE Eur Solid-State Circuits Conf (ESSCIRC)"},{"key":"ref11","first-page":"282","article-title":"A 5 mW 7b 2.4 GS\/s 1-then-2b\/cycle SAR ADC with background offset calibration","author":"chan","year":"2017","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2016.7418106"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2198773"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2305075"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2016.2594256"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2016.2554798"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2006232"},{"key":"ref18","first-page":"1","article-title":"A 5.5 mW 6b 5 GS\/S 4\n$\\times$\n-lnterleaved 3b\/cycle SAR ADC in 65 nm CMOS","author":"chan","year":"2015","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref19","first-page":"162c","article-title":"A 6b 46 GS\/s ADC with >23 GHz BW and sparkle-code error correction","author":"duan","year":"2015","journal-title":"IEEE Symp VLSI Circuits Dig Tech Papers"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2013.6649086"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2014.6757479"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2279571"},{"key":"ref6","first-page":"470","article-title":"A 2.6b\/cycle-architecture-based 10b 1 JGS\/s 15.4 mW 4\n$\\times$\n-time-interleaved SAR ADC with a multistep hardware-retirement technique","author":"hong","year":"2015","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref5","first-page":"188","article-title":"A 0.024 mm2 8b 400 MS\/s SAR ADC with 605 2b\/cycle and resistive DAC in 65 nm CMOS","author":"wei","year":"2011","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref8","first-page":"466","article-title":"A 1.7 mW11 b 250 MS\/s 2\n$\\times$\n interleaved fully dynamic pipelined SAR ADC in 40 nm digital CMOS","author":"verbruggen","year":"2012","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2204543"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2012.6243803"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2016.2559513"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.884231"},{"key":"ref20","first-page":"284","article-title":"An 8 GS\/s time-interleaved SAR ADC with unresolved decision detection achieving ?58 dBFS noise and 4 GHz bandwidth in 28 nm CMOS","author":"keane","year":"2017","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/4.508260"},{"key":"ref21","first-page":"1","article-title":"A 6-bit 0.81 mW 700-MS\/s SAR ADC with sparkle-code correction, resolution enhancement, and background window width calibration","author":"yoon","year":"2017","journal-title":"Proc IEEE Custom Integr Circuits Conf (CICC)"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1002\/9780470374122"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2185352"},{"key":"ref26","first-page":"314","article-title":"A double-tail latch-type voltage sense amplifier with 18 ps setup+hold time","author":"shinkel","year":"2007","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref25","first-page":"241","article-title":"A 1V 11 fJ\/conversion-step 10 bit 10 MS\/s asynchronous SAR ADC in 0.18 \n$\\mu $\nm CMOS","author":"liu","year":"2010","journal-title":"IEEE Symp VLSI Circuits Dig Tech Papers"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/ieeexplore.ieee.org\/ielaam\/4\/8295182\/8169683-aam.pdf","content-type":"application\/pdf","content-version":"am","intended-application":"syndication"},{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/8295182\/08169683.pdf?arnumber=8169683","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,4,8]],"date-time":"2022-04-08T18:55:49Z","timestamp":1649444149000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/8169683\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,3]]},"references-count":27,"journal-issue":{"issue":"3"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2017.2768404","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2018,3]]}}}