{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,15]],"date-time":"2026-04-15T17:47:05Z","timestamp":1776275225454,"version":"3.50.1"},"reference-count":12,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2018,4,1]],"date-time":"2018-04-01T00:00:00Z","timestamp":1522540800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"name":"U.S. Government"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2018,4]]},"DOI":"10.1109\/jssc.2017.2773637","type":"journal-article","created":{"date-parts":[[2017,12,6]],"date-time":"2017-12-06T19:17:48Z","timestamp":1512587868000},"page":"1038-1048","source":"Crossref","is-referenced-by-count":47,"title":["A Digitally Controlled Fully Integrated Voltage Regulator With 3-D-TSV-Based On-Die Solenoid Inductor With a Planar Magnetic Core for 3-D-Stacked Die Applications in 14-nm Tri-Gate CMOS"],"prefix":"10.1109","volume":"53","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-5927-8339","authenticated-orcid":false,"given":"Harish K.","family":"Krishnamurthy","sequence":"first","affiliation":[]},{"given":"Sheldon","family":"Weng","sequence":"additional","affiliation":[]},{"given":"George E.","family":"Mathew","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6795-6440","authenticated-orcid":false,"given":"Nachiket","family":"Desai","sequence":"additional","affiliation":[]},{"given":"Ruchir","family":"Saraswat","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2271-4314","authenticated-orcid":false,"given":"Krishnan","family":"Ravichandran","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0317-4332","authenticated-orcid":false,"given":"James W.","family":"Tschanz","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5207-1079","authenticated-orcid":false,"given":"Vivek","family":"De","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","first-page":"1","article-title":"A 500 MHz, 68% efficient, fully on-die digitally controlled buck voltage regulator on 22 nm Tri-Gate CMOS","author":"krishnamurthy","year":"2014","journal-title":"VLSI Dig Tech Papers"},{"key":"ref3","first-page":"336","article-title":"A digitally controlled fully integrated voltage regulator with on-die solenoid inductor with planar magnetic core in 14 nm Tri-Gate CMOS","author":"krishnamurthy","year":"2017","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref10","first-page":"17","article-title":"A fully-integrated 0.18 $\\mu $ m CMOS DC-DC step-down converter, using a bondwire spiral inductor","author":"wens","year":"2008","journal-title":"Proc IEEE CICC"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2157253"},{"key":"ref11","first-page":"1","article-title":"Optimal design of monolithic integrated DC-DC converters","author":"schrom","year":"2006","journal-title":"Proc ICIDT"},{"key":"ref5","first-page":"35.3.1","article-title":"High-Q magnetic inductors for high efficiency on-chip power conversion","author":"wang","year":"2017","journal-title":"IEDM Tech Dig"},{"key":"ref12","doi-asserted-by":"crossref","first-page":"319","DOI":"10.1109\/TCSII.2005.859572","article-title":"A high efficiency, soft switching DC-DC converter with adaptive current-ripple control for portable applications","volume":"53","author":"xiao","year":"2006","journal-title":"IEEE Trans Circuits Syst II Exp Briefs"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2274826"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2131770"},{"key":"ref2","first-page":"432","article-title":"FIVR&#x2014;Fully integrated voltage regulators on 4th generation Intel Core SoCs","author":"burton","year":"2014","journal-title":"Proc APEC"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TPEL.2008.2009986"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2221237"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/8325040\/08168829.pdf?arnumber=8168829","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:23:13Z","timestamp":1642004593000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/8168829\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,4]]},"references-count":12,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2017.2773637","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2018,4]]}}}