{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,31]],"date-time":"2026-01-31T05:36:25Z","timestamp":1769837785615,"version":"3.49.0"},"reference-count":39,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"2","license":[{"start":{"date-parts":[[2018,2,1]],"date-time":"2018-02-01T00:00:00Z","timestamp":1517443200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"name":"Systems on Nanoscale Information fabriCs (SONIC), one of the six SRC STARnet Centers, sponsored by SRC and DARPA"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2018,2]]},"DOI":"10.1109\/jssc.2017.2782087","type":"journal-article","created":{"date-parts":[[2018,1,4]],"date-time":"2018-01-04T22:57:16Z","timestamp":1515106636000},"page":"642-655","source":"Crossref","is-referenced-by-count":205,"title":["A Multi-Functional In-Memory Inference Processor Using a Standard 6T SRAM Array"],"prefix":"10.1109","volume":"53","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-8104-5136","authenticated-orcid":false,"given":"Mingu","family":"Kang","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4743-6461","authenticated-orcid":false,"given":"Sujan K.","family":"Gonugondla","sequence":"additional","affiliation":[]},{"given":"Ameya","family":"Patil","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4323-9164","authenticated-orcid":false,"given":"Naresh R.","family":"Shanbhag","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref39","author":"lecun","year":"2010"},{"key":"ref38","author":"crate","year":"2016","journal-title":"Gun Shot Sounds"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1038\/nature16961"},{"key":"ref32","first-page":"65","article-title":"A functional \n$0.69~\\mu $\nm2 embedded 6T-SRAM bit cell for 65 nm CMOS platform","author":"arnaud","year":"2003","journal-title":"IEEE Symp VLSI Technol Dig Tech Papers"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/16.628833"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/ASSCC.2016.7844125"},{"key":"ref37","year":"2000","journal-title":"Center for Biological and Computational Learning at MIT"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2213513"},{"key":"ref35","article-title":"Circuits and methods of a self-timed high speed SRAM","author":"chung","year":"2015"},{"key":"ref34","first-page":"1737","article-title":"Deep learning with limited numerical precision","author":"gupta","year":"2015","journal-title":"Proc ICML"},{"key":"ref10","first-page":"248","article-title":"A 0.62 mW ultra-low-power convolutional-neural-network face-recognition processor and a CIS integrated with always-on Haar-like face detector","author":"bong","year":"2017","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref11","first-page":"10","article-title":"Computing’s energy problem (and what we can do about it)","author":"horowitz","year":"2014","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/2541940.2541967"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ACSSC.2015.7421361"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001177"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2003.1253179"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.897148"},{"key":"ref17","first-page":"332","article-title":"A sub-200 mV 6T SRAM in 0.13 \n$\\mu $\nm CMOS","author":"zhai","year":"2007","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2408332"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2015.2503733"},{"key":"ref28","author":"kang","year":"2016","journal-title":"A 481 pJ\/decision 3 4 M decision\/s multifunctional deep in-memory inference processor using standard 6T SRAM array"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2007157"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2642198"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2015.7062935"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2280238"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2007.4418976"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2031768"},{"key":"ref8","first-page":"242","article-title":"A 28 nm SoC with a 1.2 GHz 568 nJ\/prediction sparse deep-neural-network engine with >0.1 timing error rate tolerance for IoT applications","author":"whatmough","year":"2017","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2017.7870352"},{"key":"ref2","first-page":"260","article-title":"A 21.5 M-query-vectors\/s 3.37 nJ\/vector reconfigurable k-nearest-neighbor accelerator with adaptive precision in 14 nm tri-gate CMOS","author":"kaul","year":"2016","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref9","first-page":"246","article-title":"Envision: A 0.26-to-10 TOPS\/W subword-parallel dynamic-voltage-accuracy-frequency-scalable convolutional neural network processor in 28 nm FDSOI","author":"moons","year":"2017","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2616357"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TNN.2003.816345"},{"key":"ref22","article-title":"Compute memory","author":"shanbhag","year":"2017"},{"key":"ref21","first-page":"8326","article-title":"An energy-efficient VLSI architecture for pattern recognition via deep embedding of computation in SRAM","author":"kang","year":"2014","journal-title":"Proc IEEE Int Conf Acoust Speech Signal Process (ICASSP)"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2015.7169194"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ICASSP.2015.7178127"},{"key":"ref26","first-page":"263","article-title":"A 19.4 nJ\/decision 364 K decisions\/s in-memory random forest classifier in 6T SRAM array","author":"kang","year":"2017","journal-title":"Proc IEEE Eur Solid-State Circuits Conf (ESSCIRC)"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TBCAS.2016.2545402"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/8271882\/08246704.pdf?arnumber=8246704","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:24:48Z","timestamp":1642004688000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/8246704\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,2]]},"references-count":39,"journal-issue":{"issue":"2"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2017.2782087","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2018,2]]}}}