{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,1]],"date-time":"2026-04-01T17:55:33Z","timestamp":1775066133197,"version":"3.50.1"},"reference-count":21,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"3","license":[{"start":{"date-parts":[[2018,3,1]],"date-time":"2018-03-01T00:00:00Z","timestamp":1519862400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/501100001809","name":"NSFC","doi-asserted-by":"publisher","award":["61604180"],"award-info":[{"award-number":["61604180"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Macau Science and Technology Development Fund","award":["117\/2016\/A3"],"award-info":[{"award-number":["117\/2016\/A3"]}]},{"DOI":"10.13039\/501100004733","name":"University of Macau","doi-asserted-by":"publisher","award":["MYRG2015-0086-AMSV"],"award-info":[{"award-number":["MYRG2015-0086-AMSV"]}],"id":[{"id":"10.13039\/501100004733","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2018,3]]},"DOI":"10.1109\/jssc.2017.2785349","type":"journal-article","created":{"date-parts":[[2018,1,18]],"date-time":"2018-01-18T19:35:15Z","timestamp":1516304115000},"page":"850-860","source":"Crossref","is-referenced-by-count":74,"title":["A Two-Way Interleaved 7-b 2.4-GS\/s 1-Then-2 b\/Cycle SAR ADC With Background Offset Calibration"],"prefix":"10.1109","volume":"53","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-7635-1101","authenticated-orcid":false,"given":"Chi-Hang","family":"Chan","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8298-3244","authenticated-orcid":false,"given":"Yan","family":"Zhu","sequence":"additional","affiliation":[]},{"given":"Wai-Hong","family":"Zhang","sequence":"additional","affiliation":[]},{"given":"Seng-Pan","family":"U","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2821-648X","authenticated-orcid":false,"given":"Rui Paulo","family":"Martins","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.884231"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2048498"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2006315"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.848021"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2139530"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1975.1050629"},{"key":"ref16","first-page":"417","article-title":"A 1.4 mW 8b 350 MS\/s loop-unrolled SAR ADC with background offset calibration in 40 nm CMOS","author":"ragab","year":"2016","journal-title":"Proc Eur Solid-State Circuits Conf ESSCIRC"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2014.2387532"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2108125"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2264617"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2012329"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2279571"},{"key":"ref6","first-page":"1","article-title":"A 5.5 mW 6b 5GS\/S 4\n$\\times$\n-lnterleaved 3b\/cycle SAR ADC in 65 nm CMOS","author":"chan","year":"2015","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2364833"},{"key":"ref8","first-page":"86","article-title":"A 3.8 mW 8b 1 GS\/s 2b\/cycle interleaving SAR ADC with compact DAC structure","author":"chan","year":"2012","journal-title":"Proc VLSI Circuits (VLSIC) Symp"},{"key":"ref7","first-page":"282","article-title":"A 5 mW7b 2.4 GS\/s 1-then-2b\/cycle SAR ADC with background offset calibration","author":"chan","year":"2017","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2014.6757482"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2519397"},{"key":"ref9","first-page":"1","article-title":"A 21fJ\/conv-step 9 ENOB 1.6 GS\/S \n$2\\times$\n time-interleaved FATI SAR ADC with background offset and timing-skew calibration in 45 nm CMOS","author":"sung","year":"0","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2143870"},{"key":"ref21","first-page":"204","article-title":"A 8.2-mW 10-b 1.6-GS\/s \n$4\\times $\n TI SAR ADC with fast reference charge neutralization and background timing-skew calibration in 16-nm CMOS","author":"lin","year":"2016","journal-title":"Proc IEEE Symp VLSI Circuits (VLSIC)"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/8295182\/08263405.pdf?arnumber=8263405","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:23:00Z","timestamp":1642004580000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/8263405\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,3]]},"references-count":21,"journal-issue":{"issue":"3"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2017.2785349","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2018,3]]}}}