{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,21]],"date-time":"2026-04-21T15:17:49Z","timestamp":1776784669007,"version":"3.51.2"},"reference-count":46,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"3","license":[{"start":{"date-parts":[[2018,3,1]],"date-time":"2018-03-01T00:00:00Z","timestamp":1519862400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2018,3]]},"DOI":"10.1109\/jssc.2017.2788872","type":"journal-article","created":{"date-parts":[[2018,1,18]],"date-time":"2018-01-18T19:35:15Z","timestamp":1516304115000},"page":"738-749","source":"Crossref","is-referenced-by-count":38,"title":["A Reconfigurable Vernier Time-to-Digital Converter With 2-D Spiral Comparator Array and Second-Order $\\Delta \\Sigma$ Linearization"],"prefix":"10.1109","volume":"53","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-8437-7726","authenticated-orcid":false,"given":"Hechen","family":"Wang","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0003-1691-6649","authenticated-orcid":false,"given":"Fa Foster","family":"Dai","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4952-5505","authenticated-orcid":false,"given":"Hua","family":"Wang","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref39","first-page":"136c","article-title":"A 9 b, 1.12 ps resolution 2.5 b\/stage pipelined time-to-digital converter in 65 nm CMOS using time-register","author":"kim","year":"2013","journal-title":"IEEE Int Symp VLSI Circuits Dig"},{"key":"ref38","first-page":"1","article-title":"A 0.63 ps, 12 b, synchronous cyclic TDC using a time adder for on-chip jitter measurement of a SoC in 28 nm CMOS technology","author":"kim","year":"2014","journal-title":"IEEE Int Symp VLSI Circuits Dig"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2015.2447001"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/RFIC.2016.7508269"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.843604"},{"key":"ref30","author":"rogers","year":"2006","journal-title":"Integrated Circuit Design for High-Speed Frequency Synthesis"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2305651"},{"key":"ref36","doi-asserted-by":"crossref","first-page":"357","DOI":"10.1109\/JSSC.2015.2492781","article-title":"A 2.02&#x2013;5.16 fJ\/conversion step 10-bit hybrid coarse-fine SAR ADC with time-domain quantizer in 90 nm CMOS","volume":"51","author":"chen","year":"2016","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref35","first-page":"336","article-title":"A 65 nm CMOS ADPLL with 360 $\\mu \\text{W}$ 1.6 ps-INL SS-ADC-based period-detection-free TDC","author":"sai","year":"2016","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref34","first-page":"1","article-title":"A 0.6 V 1.17 ps PVT-tolerant and synthesizable time-to-digital converter using stochastic phase interpolation with $16\\times $ spatial redundancy in 14 nm FinFET technology","author":"kim","year":"2015","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2076591"},{"key":"ref40","first-page":"192","article-title":"A 7 b, 3.75 ps resolution two-step time-to-digital converter in 65 nm CMOS using pulse-train time amplifier","author":"kim","year":"2012","journal-title":"IEEE Int Symp VLSI Circuits Dig"},{"key":"ref11","first-page":"422","article-title":"A 14 nm fractional-N digital PLL with 0.14 psrms jitter and 78 dBc fractional spur for cellular RFICs","author":"yao","year":"2017","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2682841"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2413846"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2385753"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2557807"},{"key":"ref16","article-title":"Frequency modulated phase locked loop with fractional divider and jitter compensation","author":"wheatley","year":"1991"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/RFIC.2005.1489847"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/4.823449"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2040306"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2638882"},{"key":"ref4","first-page":"439","article-title":"Fully integrated frequency and phase generation for a 6&#x2013;18 GHz tunable multi-band phased-array receiver in CMOS","author":"bohn","year":"2008","journal-title":"Proc IEEE RFIC Symp Dig Papers"},{"key":"ref27","first-page":"1","article-title":"A 3-dimensional Vernier ring time-to-digital converter in $0.13\\mu \\text{m}$ CMOS","author":"yu","year":"2010","journal-title":"Proc IEEE Custom Integr Circuits Conf (CICC) Dig Papers"},{"key":"ref3","first-page":"1","article-title":"A 28 nm CMOS digital fractional-N PLL with&#x2013;245.5 dB FOM and a frequency tripler for 802.11 abgn\/AC radio","author":"gao","year":"2015","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref6","first-page":"392","article-title":"A 2.2 GHz 7.6 mW sub-sampling PLL with&#x2013;126 dBc\/Hz in-band phase noise and 0.15psrms jitter in 0.18 $\\mu \\text{m}$ CMOS","author":"gao","year":"2009","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref29","first-page":"1","article-title":"A 330 $\\mu \\text{W}$ 1.25 ps 400 fs-INL Vernier time-to-digital converter with 2D reconfigurable spiral arbiter array and $2\\rm ^{nd}$ -order $\\Delta \\Sigma $ linearization","author":"wang","year":"2017","journal-title":"Proc IEEE Custom Integr Circuits Conf (CICC) Dig Papers"},{"key":"ref5","first-page":"2442","article-title":"A 6.25 GHz 1 V LC-PLL in 0.13 $\\mu \\text{m}$ CMOS","author":"gu","year":"2006","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.857417"},{"key":"ref7","author":"zhao","year":"2014","journal-title":"Low-Noise Low-Power Design for Phase-Locked Loops Multi-Phase High-Performance Oscillators"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2217854"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2005704"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.836345"},{"key":"ref46","first-page":"304","article-title":"A packaged 90-to-300 GHz transmitter and 115-to-325 GHz coherent receiver in CMOS for full-band continuous-wave mm-wave hyperspectral imaging","author":"chi","year":"2017","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref20","first-page":"143","article-title":"A 14-Bit, 1-ps resolution, two-step ring and 2D Vernier TDC in 130 nm CMOS technology","author":"wang","year":"2017","journal-title":"Proc IEEE Eur Solid-State Circuits Conf (ESSCIRC)"},{"key":"ref45","first-page":"296","article-title":"183 GHz 13.5 mW\/pixel CMOS regenerative receiver for mm-wave imaging applications","author":"tang","year":"2011","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2399673"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2013.6658465"},{"key":"ref42","first-page":"152","article-title":"A 0.63 ps resolution, 11 b pipeline TDC in 0.13 $\\mu \\text{m}$ CMOS","author":"seo","year":"2011","journal-title":"IEEE Int Symp VLSI Circuits Dig"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2297412"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2176609"},{"key":"ref23","first-page":"168","article-title":"A 9b, 1.25 ps resolution coarse-fine time-to-digital converter in 90 nm CMOS that amplifies a time residue","author":"lee","year":"2007","journal-title":"Proc IEEE Int Symp VLSI Circuits Dig"},{"key":"ref44","first-page":"1","article-title":"A bidirectional lens-free digital-bits-in\/-out 0.57 mm2 terahertz nano-radio in CMOS with 49.3 mW peak power consumption supporting 50 cm Internet-of-Things communication","author":"chi","year":"2017","journal-title":"Proc IEEE Custom Integr Circuits Conf (CICC) Dig Papers"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2047435"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.917405"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2014709"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/8295182\/08263415.pdf?arnumber=8263415","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:23:00Z","timestamp":1642004580000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/8263415\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,3]]},"references-count":46,"journal-issue":{"issue":"3"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2017.2788872","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2018,3]]}}}