{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,4]],"date-time":"2026-03-04T17:05:11Z","timestamp":1772643911675,"version":"3.50.1"},"reference-count":25,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"6","license":[{"start":{"date-parts":[[2018,6,1]],"date-time":"2018-06-01T00:00:00Z","timestamp":1527811200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/100000006","name":"U.S. Office of Naval Research (ONR)","doi-asserted-by":"publisher","award":["N00014-11-1-0819"],"award-info":[{"award-number":["N00014-11-1-0819"]}],"id":[{"id":"10.13039\/100000006","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2018,6]]},"DOI":"10.1109\/jssc.2018.2808244","type":"journal-article","created":{"date-parts":[[2018,5,9]],"date-time":"2018-05-09T19:02:11Z","timestamp":1525892531000},"page":"1765-1779","source":"Crossref","is-referenced-by-count":72,"title":["A 12-Bit 1.6, 3.2, and 6.4 GS\/s 4-b\/Cycle Time-Interleaved SAR ADC With Dual Reference Shifting and Interpolation"],"prefix":"10.1109","volume":"53","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-0986-4107","authenticated-orcid":false,"given":"Jae-Won","family":"Nam","sequence":"first","affiliation":[]},{"given":"Mohsen","family":"Hassanpourghadi","sequence":"additional","affiliation":[]},{"given":"Aoyang","family":"Zhang","sequence":"additional","affiliation":[]},{"given":"Mike Shuo-Wei","family":"Chen","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","first-page":"464","article-title":"A 21 fJ\/conv-step 9 ENOB 1.6 GS\/S 2\n$\\times$\n timeinterleaved FATI SAR ADC with background offset and timing-skew calibration in 45 nm CMOS","author":"sung","year":"2015","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2519397"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2016.7418108"},{"key":"ref13","first-page":"466","article-title":"A 14 b 2.5 GS\/s 8-way interleaved pipelined ADC with background calibration and digital dynamic linearity correction","author":"setterberg","year":"2013","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref14","first-page":"1","article-title":"A 14.6 mW 12 b 800 MS\/s \n$4\\times $\ntime-interleaved pipelined SAR ADC achieving 60.8 dB SNDR with Nyquist input and sampling timing skew of 60fsrms without calibration","author":"lien","year":"2016","journal-title":"Symp VLSI Circuits Dig Tech Papers"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2012329"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2214181"},{"key":"ref17","doi-asserted-by":"crossref","first-page":"365","DOI":"10.1109\/JSSC.2015.2493167","article-title":"A 6 b 5 GS\/s 4 interleaved 3 b\/cycle SAR ADC","volume":"51","author":"chan","year":"2016","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref18","first-page":"470","article-title":"A 2.6 b\/cycle-architecture-based 10 b 1 JGS\/s 15.4 mW 4\n$\\times$\n-time-interleaved SAR ADC with a multistep hardwareretirement technique","author":"hong","year":"2015","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref19","first-page":"282","article-title":"5 mW 7 b 2.4 GS\/s 1-then-2 b\/cycle SAR ADC with background offset calibration","author":"chan","year":"2017","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2003.1234315"},{"key":"ref3","first-page":"468","article-title":"A 5 GS\/S 150 mW 10 b SHA-less pipelined\/SAR hybrid ADC in 28 nm CMOS","author":"brandolini","year":"2015","journal-title":"ISSCC Dig Tech Papers"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2061611"},{"key":"ref5","first-page":"1","article-title":"A 12-bit 1.6 GS\/s interleaved SAR ADC with dual reference shifting and interpolation achieving 17.8 fJ\/conv-step in 65 nm CMOS","author":"nam","year":"2016","journal-title":"Symp VLSI Circuits Dig Tech Papers"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2239005"},{"key":"ref7","first-page":"180","article-title":"A 480 mW 2.6 GS\/s 10 b time-interleaved ADC with 48.5 dB SNDR up to Nyquist in 65 nm CMOS","author":"doris","year":"2011","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref2","first-page":"206","article-title":"A 14-bit 2.5 GS\/s and 5 GS\/s RF sampling ADC with background calibration and dither","author":"ali","year":"2016","journal-title":"Symp VLSI Circuits Dig Tech Papers"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2362851"},{"key":"ref1","first-page":"466","article-title":"A 4 GS\/s 13 b pipelined ADC with capacitor and amplifier sharing in 16 nm CMOS","author":"wu","year":"2016","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2016.2587621"},{"key":"ref22","first-page":"92c","article-title":"A 5.4 GS\/s 12 b 500 mW pipeline ADC in 28 nm CMOS","author":"wu","year":"2013","journal-title":"Symp VLSI Circuits Dig Tech Papers"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.884231"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2747758"},{"key":"ref23","first-page":"276","article-title":"A 13 b 4 GS\/s digitally assisted dynamic 3-stage asynchronous pipelined-SAR ADC","author":"vaz","year":"2017","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref25","author":"murmann","year":"2017","journal-title":"ADC Performance Survey 1997-2017"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/8364639\/08356765.pdf?arnumber=8356765","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,26]],"date-time":"2022-01-26T05:13:08Z","timestamp":1643173988000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8356765\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,6]]},"references-count":25,"journal-issue":{"issue":"6"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2018.2808244","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2018,6]]}}}