{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,21]],"date-time":"2026-02-21T20:36:50Z","timestamp":1771706210586,"version":"3.50.1"},"reference-count":37,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"6","license":[{"start":{"date-parts":[[2018,6,1]],"date-time":"2018-06-01T00:00:00Z","timestamp":1527811200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/100000028","name":"Semiconductor Research Corporation","doi-asserted-by":"publisher","award":["1830.125"],"award-info":[{"award-number":["1830.125"]}],"id":[{"id":"10.13039\/100000028","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Analog Device"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2018,6]]},"DOI":"10.1109\/jssc.2018.2810184","type":"journal-article","created":{"date-parts":[[2018,3,22]],"date-time":"2018-03-22T18:07:15Z","timestamp":1521742035000},"page":"1818-1829","source":"Crossref","is-referenced-by-count":36,"title":["A 6.75\u20138.25-GHz \u2212250-dB FoM Rapid ON\/OFF Fractional-N Injection-Locked Clock Multiplier"],"prefix":"10.1109","volume":"53","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-3252-8585","authenticated-orcid":false,"given":"Ahmed","family":"Elkholy","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ahmed","family":"Elmallah","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2636-4713","authenticated-orcid":false,"given":"Mostafa Gamal","family":"Ahmed","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Pavan Kumar","family":"Hanumolu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2539344"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2015.7063029"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2403373"},{"key":"ref30","first-page":"272","article-title":"A 20-to-1000 MHz ±14ps peak-to-peak jitter reconfigurable multi-output all-digital clock generator using open-loop fractional dividers in 65nm CMOS","author":"elkholy","year":"2014","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref37","doi-asserted-by":"crossref","first-page":"117","DOI":"10.1109\/TCSII.2008.2010189","article-title":"Jitter analysis and a benchmarking figure-of-merit for phase-locked loops","volume":"56","author":"gao","year":"2009","journal-title":"IEEE Trans Circuits Syst II Exp Briefs"},{"key":"ref36","first-page":"139","article-title":"A 2.2 GHz sub-sampling PLL with 0.16 psrms jitter and ?125dBc\/Hz in-band phase noise at 700 \n$\\mu \\text{W}$\n loop-components power","author":"gao","year":"2010","journal-title":"Proc IEEE VLSI Circuits Symp Tech Papers"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2006225"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.917372"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2016701"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2015816"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2478449"},{"key":"ref13","first-page":"336","article-title":"An all-digital clock generator using a fractionally injection-locked oscillator in 65 nm CMOS","author":"park","year":"2012","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2359670"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2473667"},{"key":"ref16","first-page":"192","article-title":"A 6.75-to-8.25 GHz, 250 fsrms-integrated-jitter 3.25 mW rapid on\/off PVT-insensitive fractional-N injection-locked clock multiplier in 65 nm CMOS","author":"elkholy","year":"2016","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2470553"},{"key":"ref18","first-page":"398","article-title":"A 16 Mb\/s-to-8 Gb\/s 14.1-to-5.9 pJ\/b source synchronous transceiver using DVFS and rapid on\/off in 65 nm CMOS","author":"shu","year":"2016","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/4.658619"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2004.834516"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2005704"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2015.7062989"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.908763"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2385753"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2361351"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2162917"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2013.6658471"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.870766"},{"key":"ref2","first-page":"1","article-title":"A fully-adaptive wideband 0.5–32.75 Gb\/s FPGA transceiver in 16 nm FinFET CMOS technology","author":"upadhyaya","year":"2016","journal-title":"Proc IEEE VLSI Circuits Symp Tech Papers"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2394323"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2217856"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2013.2252654"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2314436"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2014.2321200"},{"key":"ref24","first-page":"414","article-title":"A divider-less sub-harmonically injection-locked PLL with self-adjusted injection timing","author":"lee","year":"2013","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2227609"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2574804"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2284651"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/8364639\/08322411.pdf?arnumber=8322411","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,26]],"date-time":"2022-01-26T02:49:50Z","timestamp":1643165390000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8322411\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,6]]},"references-count":37,"journal-issue":{"issue":"6"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2018.2810184","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2018,6]]}}}