{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,8,30]],"date-time":"2025-08-30T17:12:37Z","timestamp":1756573957506,"version":"3.37.3"},"reference-count":21,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"9","license":[{"start":{"date-parts":[[2018,9,1]],"date-time":"2018-09-01T00:00:00Z","timestamp":1535760000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/501100000038","name":"Natural Sciences and Engineering Research Council of Canada","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100000038","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2018,9]]},"DOI":"10.1109\/jssc.2018.2839038","type":"journal-article","created":{"date-parts":[[2018,6,29]],"date-time":"2018-06-29T18:49:44Z","timestamp":1530298184000},"page":"2696-2708","source":"Crossref","is-referenced-by-count":19,"title":["Loop Gain Adaptation for Optimum Jitter Tolerance in Digital CDRs"],"prefix":"10.1109","volume":"53","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-8670-7781","authenticated-orcid":false,"given":"Joshua","family":"Liang","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0970-6897","authenticated-orcid":false,"given":"Ali","family":"Sheikholeslami","sequence":"additional","affiliation":[]},{"given":"Hirotaka","family":"Tamura","sequence":"additional","affiliation":[]},{"given":"Yuuki","family":"Ogata","sequence":"additional","affiliation":[]},{"given":"Hisakatsu","family":"Yamaguchi","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"crossref","first-page":"821","DOI":"10.1109\/JSSC.2016.2519391","article-title":"A bang bang phase-locked loop using automatic loop gain control and loop latency reduction techniques","volume":"51","author":"kuan","year":"2016","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2015.2495725"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2008.925948"},{"journal-title":"Analog Integrated Circuit Design","year":"2011","author":"chan carusone","key":"ref13"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2776307"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.875292"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2340574"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2009.5280739"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2004.840089"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2015.2423793"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2082272"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2253414"},{"key":"ref6","first-page":"122","article-title":"A 28 Gbps digital CDR with adaptive loop gain for optimum jitter tolerance","author":"liang","year":"2017","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref5","first-page":"1296","article-title":"Improving CDR performance via estimation","author":"lee","year":"2006","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.856576"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2003.819124"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2014.2309861"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2012.2220502"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2015.2435691"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.818567"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2378280"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/8449338\/08400567.pdf?arnumber=8400567","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:09:50Z","timestamp":1642003790000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8400567\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,9]]},"references-count":21,"journal-issue":{"issue":"9"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2018.2839038","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"type":"print","value":"0018-9200"},{"type":"electronic","value":"1558-173X"}],"subject":[],"published":{"date-parts":[[2018,9]]}}}