{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,11]],"date-time":"2025-11-11T22:20:00Z","timestamp":1762899600536,"version":"3.37.3"},"reference-count":31,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"10","license":[{"start":{"date-parts":[[2018,10,1]],"date-time":"2018-10-01T00:00:00Z","timestamp":1538352000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["61604180"],"award-info":[{"award-number":["61604180"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100006469","name":"Macao Science and Technology Development Fund","doi-asserted-by":"crossref","award":["077\/2017\/A2"],"award-info":[{"award-number":["077\/2017\/A2"]}],"id":[{"id":"10.13039\/501100006469","id-type":"DOI","asserted-by":"crossref"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2018,10]]},"DOI":"10.1109\/jssc.2018.2852326","type":"journal-article","created":{"date-parts":[[2018,7,24]],"date-time":"2018-07-24T23:04:13Z","timestamp":1532473453000},"page":"2783-2794","source":"Crossref","is-referenced-by-count":17,"title":["A 5.35-mW 10-MHz Single-Opamp Third-Order CT &lt;inline-formula&gt; \n                     &lt;tex-math notation=\"LaTeX\"&gt;$\\Delta\\Sigma$ &lt;\/tex-math&gt;\n                  &lt;\/inline-formula&gt; Modulator With CTC Amplifier and Adaptive Latch DAC Driver in 65-nm CMOS"],"prefix":"10.1109","volume":"53","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-5804-0230","authenticated-orcid":false,"given":"Wei","family":"Wang","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-9610-0641","authenticated-orcid":false,"given":"Yan","family":"Zhu","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7635-1101","authenticated-orcid":false,"given":"Chi-Hang","family":"Chan","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2821-648X","authenticated-orcid":false,"given":"Rui Paulo","family":"Martins","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2321063"},{"key":"ref30","first-page":"292c","article-title":"A 13-ENOB, 5 MHz BW, 3.16 mW multi-bit continuous-time \n$\\Delta \\Sigma $\n ADC in 28 nm CMOS with excess-loop-delay compensation embedded in SAR quantizer","author":"wei","year":"2015","journal-title":"Proc Symposium on in VLSI Circuits (VLSI Circuits)"},{"key":"ref10","first-page":"285","article-title":"A 5.35 mW 10 MHz bandwidth CT third-order \n$\\Delta \\Sigma $\n modulator with single Opamp achieving 79.6\/84.5 dB SNDR\/DR in 65 nm CMOS","author":"wang","year":"2017","journal-title":"Proc IEEE Asian Solid-State Circuits Conf (A-SSCC)"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2319254"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2345023"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2042244"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2221194"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2475160"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2591826"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2532345"},{"key":"ref18","first-page":"274","article-title":"A 1V 77dB-DR 72dB-SNDR 10MHz-BW 2-1 MASH CT \n$\\Delta \\Sigma \\text{M}$","author":"nowacki","year":"2016","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref19","first-page":"290c","article-title":"A 0.7 V \n$256~\\mu \\text{W}~\\Delta \\Sigma $\n modulator with passive RC integrators achieving 76 dB DR in 2 MHz BW","author":"de melo","year":"2015","journal-title":"Proc Symp VLSI Circuits (VLSI Circuits)"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2013.2268413"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2218062"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2042254"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2778284"},{"key":"ref6","first-page":"470","article-title":"A 125MHz-BW 71.9dB-SNDR VCO-based CT \n$\\Delta \\Sigma $\n ADC with segmented phase-domain ELD compensation in 16nm CMOS","author":"huang","year":"2017","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref29","first-page":"268","article-title":"A 28fJ\/conv-step CT \n$\\Delta \\Sigma $\n modulator with 78dB DR and 18MHz BW in 28nm CMOS using a highly digital multibit quantizer","author":"shu","year":"2013","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2032703"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2164964"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2571671"},{"key":"ref2","first-page":"270","article-title":"A 24.7mW 45MHz-BW 75.3 dB-SNDR SAR-assisted CT \n$\\Delta \\Sigma $\n modulator with 2nd-order noise coupling in 65nm CMOS","author":"wu","year":"2016","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2734906"},{"journal-title":"Continuous-Time Sigma-Delta A\/D Conversion","year":"2005","author":"ortmanns","key":"ref1"},{"key":"ref20","first-page":"472","article-title":"An 8mW 50MS\/s CT \n$\\Delta \\Sigma $\n modulator with 81 dB SFDR and digital background DAC linearization","author":"kauffman","year":"2011","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2014.6945987"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2017.2766527"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2466459"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.814432"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2032624"},{"key":"ref25","first-page":"92c","article-title":"A 5.4GS\/s 12b 500mW pipeline ADC in 28nm CMOS","author":"wu","year":"2013","journal-title":"Proc Symp VLSI Circuits"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/8470270\/08419079.pdf?arnumber=8419079","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,26]],"date-time":"2022-01-26T10:25:28Z","timestamp":1643192728000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8419079\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,10]]},"references-count":31,"journal-issue":{"issue":"10"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2018.2852326","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"type":"print","value":"0018-9200"},{"type":"electronic","value":"1558-173X"}],"subject":[],"published":{"date-parts":[[2018,10]]}}}