{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,9,30]],"date-time":"2026-09-30T11:54:17Z","timestamp":1790769257323,"version":"4.1.0"},"reference-count":23,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2019,1,1]],"date-time":"2019-01-01T00:00:00Z","timestamp":1546300800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,1,1]],"date-time":"2019-01-01T00:00:00Z","timestamp":1546300800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,1,1]],"date-time":"2019-01-01T00:00:00Z","timestamp":1546300800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2019,1]]},"DOI":"10.1109\/jssc.2018.2872584","type":"journal-article","created":{"date-parts":[[2018,10,16]],"date-time":"2018-10-16T18:47:30Z","timestamp":1539715650000},"page":"231-239","source":"Crossref","is-referenced-by-count":57,"title":["A 1-Mb 28-nm 1T1MTJ STT-MRAM With Single-Cap Offset-Cancelled Sense Amplifier and &lt;italic&gt;In Situ&lt;\/italic&gt; Self-Write-Termination"],"prefix":"10.1109","volume":"54","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-1380-269X","authenticated-orcid":false,"given":"Qing","family":"Dong","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Zhehong","family":"Wang","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0306-3966","authenticated-orcid":false,"given":"Jongyup","family":"Lim","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5584-6503","authenticated-orcid":false,"given":"Yiqun","family":"Zhang","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Mahmut E.","family":"Sinangil","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-1511-2366","authenticated-orcid":false,"given":"Yi-Chun","family":"Shih","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Yu-Der","family":"Chih","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jonathan","family":"Chang","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6744-7075","authenticated-orcid":false,"given":"David","family":"Blaauw","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Dennis","family":"Sylvester","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref10","first-page":"1","article-title":"A 3.3 ns-access-time \n$71.2~\\mu\\text{W}$\n\/MHz 1 Mb embedded STT-MRAM using physically eliminated read-disturb scheme and normally-off memory architecture","author":"noguchi","year":"2015","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref11","first-page":"108c","article-title":"A 250-MHz 256b-I\/O 1-Mb STT-MRAM with advanced perpendicular MTJ based dual cell for nonvolatile magnetic caches to reduce active power of processors","author":"noguchi","year":"2013","journal-title":"Proc Symp VLSI circuits (VLSI)"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2170778"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2224256"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1063\/1.2219997"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TMAG.2012.2200469"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2015.2412960"},{"key":"ref17","first-page":"1","article-title":"Asynchronous asymmetrical write termination (AAWT) for a low power STT-MRAM","author":"bishnoi","year":"2014","journal-title":"Proc Conf Design Autom Test Eur (DATE)"},{"key":"ref18","first-page":"480","article-title":"A 1 Mb 28 nm STT-MRAM with 2.8 ns read access time at 1.2V VDD using single-cap offset-cancelled sense amplifier and In-situ self-write-termination","author":"dong","year":"2018","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2235013"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.845564"},{"key":"ref3","first-page":"198","article-title":"11.2 A 1 Mb embedded NOR flash memory with \n$39~\\mu\\text{W}$\n program power for mm-scale high-temperature sensor nodes","author":"dong","year":"2017","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref6","first-page":"224","article-title":"Cycling endurance optimization scheme for 1 Mb STT-MRAM in 40 nm technology","author":"yu","year":"2013","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2016.7417942"},{"key":"ref8","first-page":"256","article-title":"Negative-resistance read and write schemes for STT-MRAM in \n$0.13~\\mu\\text{m}$\n CMOS","author":"halupka","year":"2010","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref7","first-page":"258","article-title":"A 64 Mb MRAM with clamped-reference and adequate-reference schemes","author":"tsuchida","year":"2010","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2661838"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2776309"},{"key":"ref9","first-page":"462","article-title":"A 90 nm 12 ns 32 Mb 2T1MTJ MRAM","author":"nebashi","year":"2009","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref20","first-page":"424","article-title":"A 45 nm self-aligned-contact process 1Gb NOR flash with 5 MB\/s program speed","author":"javanifard","year":"2008","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2612235"},{"key":"ref21","doi-asserted-by":"crossref","first-page":"557","DOI":"10.1109\/JSSC.2015.2498302","article-title":"A 28 nm 2 Mbit 6 T SRAM with highly configurable low-voltage write-ability assist implementation and capacitor-based sense-amplifier input offset compensation","volume":"51","author":"sinangil","year":"2016","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref23","first-page":"242","article-title":"A reconfigurable sense amplifier with auto-zero calibration and pre-amplification in 28 nm CMOS","author":"giridhar","year":"2013","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/8613098\/08493263.pdf?arnumber=8493263","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,13]],"date-time":"2022-07-13T20:58:40Z","timestamp":1657745920000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8493263\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,1]]},"references-count":23,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2018.2872584","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2019,1]]}}}