{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,8]],"date-time":"2026-07-08T15:54:44Z","timestamp":1783526084610,"version":"3.55.0"},"reference-count":19,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2019,1,1]],"date-time":"2019-01-01T00:00:00Z","timestamp":1546300800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,1,1]],"date-time":"2019-01-01T00:00:00Z","timestamp":1546300800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,1,1]],"date-time":"2019-01-01T00:00:00Z","timestamp":1546300800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"name":"DARPA CRAFT Program, U.S. Government"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2019,1]]},"DOI":"10.1109\/jssc.2018.2875092","type":"journal-article","created":{"date-parts":[[2018,11,9]],"date-time":"2018-11-09T22:49:34Z","timestamp":1541803774000},"page":"43-54","source":"Crossref","is-referenced-by-count":69,"title":["A 1.17-pJ\/b, 25-Gb\/s\/pin Ground-Referenced Single-Ended Serial Link for Off- and On-Package Communication Using a Process- and Temperature-Adaptive Voltage Regulator"],"prefix":"10.1109","volume":"54","author":[{"given":"John W.","family":"Poulton","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8488-3020","authenticated-orcid":false,"given":"John M.","family":"Wilson","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9230-7605","authenticated-orcid":false,"given":"Walker J.","family":"Turner","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Brian","family":"Zimmer","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7368-4787","authenticated-orcid":false,"given":"Xi","family":"Chen","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Sudhir S.","family":"Kudva","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Sanquan","family":"Song","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Stephen G.","family":"Tell","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Nikola","family":"Nedovic","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-9239-9797","authenticated-orcid":false,"given":"Wenxu","family":"Zhao","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Sunil R.","family":"Sudhakaran","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5137-5617","authenticated-orcid":false,"given":"C. Thomas","family":"Gray","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"William J.","family":"Dally","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref10","first-page":"274","article-title":"A 126 mW 56 Gb\/s NRZ wireline transceiver for synchronous short-reach applications in 16 nm FinFET","author":"erett","year":"2018","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref11","first-page":"182","article-title":"A pin-efficient 20.83 Gb\/s\/wire 0.94 pJ\/bit forwarded clock CNRZ-5-coded SerDes up to 12 mm for MCM packages in 28 nm CMOS","author":"shokrollahi","year":"2016","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2279053"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2018.8310291"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2018.8357077"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2018.8357021"},{"key":"ref16","article-title":"MOSFET sense amplifier circuit","author":"johnson","year":"1983"},{"key":"ref17","first-page":"1","article-title":"A 25 Gb\/s 470 \n$\\mu\\text{W}$\n active inductor equalizer for ground referenced signaling receivers","author":"fick","year":"2017","journal-title":"Proc Int Symp Circuits Syst"},{"key":"ref18","author":"yuan","year":"2008","journal-title":"CMOS Active Inductors and Transformers Principle Implementation and Applications"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2076214"},{"key":"ref4","first-page":"110","article-title":"A 64 Gb\/s PAM-4 transceiver utilizing an adaptive threshold ADC in 16 nm FinFET","author":"wang","year":"2018","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2018.8310207"},{"key":"ref6","first-page":"114","article-title":"A 40-to-56 Gb\/s PAM-4 receiver with 10-tap direct decision-feedback equalization in 16nm FinFET","author":"im","year":"2017","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref5","first-page":"118","article-title":"A 1.8 pJ\/b 56 Gb\/s PAM-4 transmitter with fractionally spaced FFE in 14nm CMOS","author":"dickson","year":"2017","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref8","author":"o\u2019connor","year":"2014","journal-title":"Highlights of the High Bandwidth Memory (HBM) Standard The Memory Forum"},{"key":"ref7","first-page":"64","article-title":"A 56 Gb\/s NRZ-electrical 247 mW\/lane serial-link transceiver in 28 nm CMOS","author":"shibasaki","year":"2016","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref2","year":"2017","journal-title":"OIF-CEI-03 0-Common Electrical I\/O (CEI)-Electrical and Jitter Interoperability Agreements for 6G+ Bps 11G+ Bps 25G+ Bps I\/O"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2017.2717900"},{"key":"ref9","first-page":"112","article-title":"A 4.9 pJ\/b 16-to-64 Gb\/s PAM-4 VSR transceiver in 28 nm FDSOI CMOS","author":"depaoli","year":"2018","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/8613098\/08528390.pdf?arnumber=8528390","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,13]],"date-time":"2022-07-13T20:58:40Z","timestamp":1657745920000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8528390\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,1]]},"references-count":19,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2018.2875092","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2019,1]]}}}