{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T10:03:18Z","timestamp":1740132198717,"version":"3.37.3"},"reference-count":11,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2019,4,1]],"date-time":"2019-04-01T00:00:00Z","timestamp":1554076800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,4,1]],"date-time":"2019-04-01T00:00:00Z","timestamp":1554076800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,4,1]],"date-time":"2019-04-01T00:00:00Z","timestamp":1554076800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2019,4]]},"DOI":"10.1109\/jssc.2018.2889704","type":"journal-article","created":{"date-parts":[[2019,1,15]],"date-time":"2019-01-15T19:58:32Z","timestamp":1547582312000},"page":"1086-1095","source":"Crossref","is-referenced-by-count":5,"title":["A 12.8-Gb\/s Daisy Chain-Based Downlink I\/F Employing Spectrally Compressed Multi-Band Multiplexing for High-Bandwidth, Large-Capacity Storage Systems"],"prefix":"10.1109","volume":"54","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-6607-573X","authenticated-orcid":false,"given":"Yuta","family":"Tsubouchi","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2108-3397","authenticated-orcid":false,"given":"Daisuke","family":"Miyashita","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0197-9447","authenticated-orcid":false,"given":"Takashi","family":"Toi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yuji","family":"Satoh","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6311-9215","authenticated-orcid":false,"given":"Fumihiko","family":"Tachibana","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Junji","family":"Wadatsumi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Makoto","family":"Morimoto","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ryuichi","family":"Fujimoto","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3414-5537","authenticated-orcid":false,"given":"Jun","family":"Deguchi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","first-page":"1","article-title":"1 GB\/s 2 Tb NAND flash multi-chip package with frequency-boosting interface chip","author":"kim","year":"2015","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.3389\/fnana.2016.00062"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/MSP.2011.940267"},{"key":"ref6","first-page":"1","article-title":"Fully-buffered DIMM technology moves enterprise platforms to the next level","author":"haas","year":"2005","journal-title":"Technol Intel Mag"},{"key":"ref11","first-page":"330","article-title":"66.3KIOPS-random-read 690 MB\/s-sequential-read universal Flash storage device controller with unified memory extension","author":"watanabe","year":"2014","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref5","first-page":"194c","article-title":"A 1.2 V 1.33 Gb\/s\/pin 8 Tb NAND flash memory multi-chip package employing F-chip for low power and high performance storage applications","author":"kim","year":"2017","journal-title":"Proc Symp VLSI Circuits"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2017.2763199"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2018.8502340"},{"key":"ref2","first-page":"338","article-title":"A flash memory controller for \n$15~\\mu\\text{s}$\n ultra-low-latency SSD using high-speed 3D NAND flash with \n$3~\\mu\\text{s}$\n read time","author":"cheong","year":"2018","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2628049"},{"key":"ref1","first-page":"336","article-title":"A 512 Gb 3b\/Cell 3D flash memory on a 96-word-line-layer technology","author":"maejima","year":"2018","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/8674728\/08613011.pdf?arnumber=8613011","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,13]],"date-time":"2022-07-13T21:13:11Z","timestamp":1657746791000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8613011\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,4]]},"references-count":11,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2018.2889704","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"type":"print","value":"0018-9200"},{"type":"electronic","value":"1558-173X"}],"subject":[],"published":{"date-parts":[[2019,4]]}}}