{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,3]],"date-time":"2026-06-03T16:09:55Z","timestamp":1780502995544,"version":"3.54.1"},"reference-count":26,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"6","license":[{"start":{"date-parts":[[2019,6,1]],"date-time":"2019-06-01T00:00:00Z","timestamp":1559347200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,6,1]],"date-time":"2019-06-01T00:00:00Z","timestamp":1559347200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,6,1]],"date-time":"2019-06-01T00:00:00Z","timestamp":1559347200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2019,6]]},"DOI":"10.1109\/jssc.2019.2902471","type":"journal-article","created":{"date-parts":[[2019,3,26]],"date-time":"2019-03-26T23:10:21Z","timestamp":1553641821000},"page":"1682-1693","source":"Crossref","is-referenced-by-count":17,"title":["A 25-Gb\/s Avalanche Photodetector-Based Burst-Mode Optical Receiver With 2.24-ns Reconfiguration Time in 28-nm CMOS"],"prefix":"10.1109","volume":"54","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-2968-4656","authenticated-orcid":false,"given":"Kuan Chang","family":"Chen","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6945-9958","authenticated-orcid":false,"given":"Azita","family":"Emami","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1038\/nphoton.2008.247"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ECOC.2014.6964088"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JSTQE.2017.2754361"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1002\/047174140X"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/T-ED.1966.15651"},{"key":"ref15","first-page":"130","article-title":"An 18.6 Gb\/s double-sampling receiver in 65 nm CMOS for ultra-low-power optical communication","author":"nazari","year":"2012","journal-title":"Proc IEEE Int Solid-State Circuits Conf"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2227612"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/IPEC.2012.6522643"},{"key":"ref18","first-page":"283","article-title":"A 25 Gb\/s \n$170~\\mu\\text{W}$\n\/Gb\/s optical receiver in 28 nm CMOS for chip-to-chip optical communication","author":"saeedi","year":"2014","journal-title":"Proc IEEE Radio Freq Integr Circuits Symp"},{"key":"ref19","first-page":"482","article-title":"29.1 A 64 Gb\/s 1.4 pJ\/b NRZ optical-receiver data-path in 14 nm CMOS FinFET","author":"cevrero","year":"2017","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2478837"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2018.2854372"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2553040"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2757008"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.916626"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/LPT.2018.2841841"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JLT.2015.2453092"},{"key":"ref9","author":"lee","year":"1998","journal-title":"The Design of CMOS Radio-Frequency Integrated Circuits"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JLT.2013.2279203"},{"key":"ref20","first-page":"318c","article-title":"A 32 Gb\/s, 4.7 pJ\/bit optical link with ?11.7 dBm sensitivity in 14-nm FinFET CMOS","author":"proesel","year":"2017","journal-title":"Proc Symp VLSI Circuits"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2007.373420"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2734913"},{"key":"ref24","doi-asserted-by":"crossref","first-page":"871","DOI":"10.1109\/JSSC.2016.2519389","article-title":"Design techniques for a 60 Gb\/s 173 mW wireline receiver frontend in 65 nm CMOS technology","volume":"51","author":"han","year":"2016","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2705070"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1049\/el:20081433"},{"key":"ref25","first-page":"416","article-title":"A 10 Gb\/s burst-mode TIA with on-chip reset\/lock CM signaling detection and limiting amplifier with a 75ns settling time","author":"yin","year":"2012","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/8721577\/08674615.pdf?arnumber=8674615","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,13]],"date-time":"2022-07-13T20:50:17Z","timestamp":1657745417000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8674615\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,6]]},"references-count":26,"journal-issue":{"issue":"6"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2019.2902471","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2019,6]]}}}