{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,3]],"date-time":"2026-06-03T18:20:48Z","timestamp":1780510848469,"version":"3.54.1"},"reference-count":25,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"10","license":[{"start":{"date-parts":[[2019,10,1]],"date-time":"2019-10-01T00:00:00Z","timestamp":1569888000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,10,1]],"date-time":"2019-10-01T00:00:00Z","timestamp":1569888000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,10,1]],"date-time":"2019-10-01T00:00:00Z","timestamp":1569888000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2019,10]]},"DOI":"10.1109\/jssc.2019.2917833","type":"journal-article","created":{"date-parts":[[2019,7,30]],"date-time":"2019-07-30T20:11:47Z","timestamp":1564517507000},"page":"2812-2822","source":"Crossref","is-referenced-by-count":11,"title":["A 10-Gb\/s, 0.03-mm<sup>2<\/sup>, 1.28-pJ\/bit Half-Rate Injection-Locked CDR With Path Mismatch Tracking Loop in a 28-nm CMOS Technology"],"prefix":"10.1109","volume":"54","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-8638-6332","authenticated-orcid":false,"given":"Min-Seong","family":"Choo","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4727-9868","authenticated-orcid":false,"given":"Kwanseo","family":"Park","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5184-3321","authenticated-orcid":false,"given":"Han-Gon","family":"Ko","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-1863-1719","authenticated-orcid":false,"given":"Sung-Yong","family":"Cho","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Kwangho","family":"Lee","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0436-703X","authenticated-orcid":false,"given":"Deog-Kyoon","family":"Jeong","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2478449"},{"key":"ref11","first-page":"552","article-title":"Full-rate injection-locked 10.3 Gb\/s clock and data recovery circuit in a 45 GHz-\n$\\text{f}_{T}$\n SiGe process","author":"zhan","year":"2005","journal-title":"Proc IEEE Custom Integr Circuits Conf"},{"key":"ref12","first-page":"228","article-title":"A 10 Gb\/s burst-mode CDR IC in \n$0.13~\\mu\\text{m}$\n CMOS","author":"nogawa","year":"2005","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.916598"},{"key":"ref14","first-page":"364","article-title":"A 1.296-to-5.184 Gb\/s transceiver with 2.4 mW\/(Gb\/s) burst-mode CDR using dual-edge injection-locked oscillator","author":"maruko","year":"2010","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2164023"},{"key":"ref16","first-page":"226","article-title":"A 10.3125 Gb\/s burst-mode CDR circuit using a \n$\\Delta\\Sigma$\n DAC","author":"terada","year":"2008","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2390613"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2594077"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ASSCC.2018.8579270"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/4.766813"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/4.658619"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.831608"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2002.804339"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2227609"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2010.2097652"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1049\/el:19750415"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2013.2252654"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JRPROC.1946.229930"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2007.373374"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2016.2578960"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2082272"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2011.2181547"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2465843"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1049\/el.2014.0331"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/8847474\/08781914.pdf?arnumber=8781914","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,13]],"date-time":"2022-07-13T20:50:15Z","timestamp":1657745415000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8781914\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,10]]},"references-count":25,"journal-issue":{"issue":"10"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2019.2917833","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2019,10]]}}}