{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T10:03:26Z","timestamp":1740132206800,"version":"3.37.3"},"reference-count":34,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"9","license":[{"start":{"date-parts":[[2019,9,1]],"date-time":"2019-09-01T00:00:00Z","timestamp":1567296000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,9,1]],"date-time":"2019-09-01T00:00:00Z","timestamp":1567296000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,9,1]],"date-time":"2019-09-01T00:00:00Z","timestamp":1567296000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100001459","name":"Ministry of Education - Singapore","doi-asserted-by":"publisher","award":["MOE2014-T2-2-158"],"award-info":[{"award-number":["MOE2014-T2-2-158"]}],"id":[{"id":"10.13039\/501100001459","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001381","name":"National Research Foundation Singapore","doi-asserted-by":"publisher","award":["\u201cCogniVision\u201d CRP20-2017-0006"],"award-info":[{"award-number":["\u201cCogniVision\u201d CRP20-2017-0006"]}],"id":[{"id":"10.13039\/501100001381","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2019,9]]},"DOI":"10.1109\/jssc.2019.2925269","type":"journal-article","created":{"date-parts":[[2019,7,17]],"date-time":"2019-07-17T20:13:49Z","timestamp":1563394429000},"page":"2622-2631","source":"Crossref","is-referenced-by-count":7,"title":["Reconfigurable Clock Networks for Wide Voltage Scaling"],"prefix":"10.1109","volume":"54","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-4702-737X","authenticated-orcid":false,"given":"Longyang","family":"Lin","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2724-940X","authenticated-orcid":false,"given":"Saurabh","family":"Jain","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4127-8258","authenticated-orcid":false,"given":"Massimo","family":"Alioto","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/4.231325"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.831498"},{"journal-title":"Low Power Methodology Manual For System-on-Chip Design","year":"2007","author":"keating","key":"ref31"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/4.982424"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/4.823449"},{"key":"ref10","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4419-0261-0","author":"xanthopoulos","year":"2009","journal-title":"Clocking in Modern VLSI Systems"},{"key":"ref11","doi-asserted-by":"crossref","DOI":"10.1007\/978-3-319-01997-0","author":"alioto","year":"2015","journal-title":"Flip-Flop Design in Nanometer CMOS From High Speed to Low Energy"},{"key":"ref12","first-page":"894","article-title":"Characterization of PVT variation & aging induced hold time margins of flip-flop arrays at NTV in 22 nm tri-gate CMOS","author":"augustine","year":"2016","journal-title":"IEDM Tech Dig"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1147\/rd.504.0469"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2017.2687059"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2218067"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2015.7062967"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2011.2160753"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2144595"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2190825"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2015455"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2011.2116814"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2011.2177004"},{"key":"ref3","first-page":"66","article-title":"A 280mV-to-1.2V wide-operating-range IA-32 processor in 32 nm CMOS","author":"jain","year":"2012","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ICICDT.2012.6232880"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/92.645062"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2009.2033621"},{"key":"ref8","first-page":"153","article-title":"28 nm CMOS, energy efficient and variability tolerant, 350mV-to-1.0V, 10MHz\/700MHz, 252bits frame error-decoder","author":"abouzeid","year":"2012","journal-title":"Proc ESSCIRC"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2295977"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2000.839787"},{"key":"ref9","first-page":"178","article-title":"A 280mV-to-1.1V 256b reconfigurable SIMD vector permutation engine with 2-dimensional shuffle in 22 nm CMOS","author":"hsu","year":"2012","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-51482-6"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2016.2539926"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ASSCC.2015.7387475"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/2627369.2627632"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2017.7870450"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2014.6757359"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2169311"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2768406"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/8811631\/08765351.pdf?arnumber=8765351","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,9,18]],"date-time":"2023-09-18T10:21:07Z","timestamp":1695032467000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8765351\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,9]]},"references-count":34,"journal-issue":{"issue":"9"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2019.2925269","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"type":"print","value":"0018-9200"},{"type":"electronic","value":"1558-173X"}],"subject":[],"published":{"date-parts":[[2019,9]]}}}