{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,12]],"date-time":"2026-06-12T16:31:34Z","timestamp":1781281894926,"version":"3.54.1"},"reference-count":41,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"11","license":[{"start":{"date-parts":[[2019,11,1]],"date-time":"2019-11-01T00:00:00Z","timestamp":1572566400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,11,1]],"date-time":"2019-11-01T00:00:00Z","timestamp":1572566400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,11,1]],"date-time":"2019-11-01T00:00:00Z","timestamp":1572566400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"name":"ImPACT Program of CSTI"},{"name":"Industry-Academic Collaboration of CIES Consortium through spin-transfertorque magnetoresistive random access memory (STT-MRAM) Research and Development Program"},{"DOI":"10.13039\/501100001691","name":"Japan Society for the Promotion of Science","doi-asserted-by":"publisher","award":["16KT0187"],"award-info":[{"award-number":["16KT0187"]}],"id":[{"id":"10.13039\/501100001691","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001691","name":"Japan Society for the Promotion of Science","doi-asserted-by":"publisher","award":["17KK0001"],"award-info":[{"award-number":["17KK0001"]}],"id":[{"id":"10.13039\/501100001691","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2019,11]]},"DOI":"10.1109\/jssc.2019.2930910","type":"journal-article","created":{"date-parts":[[2019,8,13]],"date-time":"2019-08-13T20:04:04Z","timestamp":1565726644000},"page":"2991-3004","source":"Crossref","is-referenced-by-count":64,"title":["A 47.14-$\\mu\\text{W}$  200-MHz MOS\/MTJ-Hybrid Nonvolatile Microcontroller Unit Embedding STT-MRAM and FPGA for IoT Applications"],"prefix":"10.1109","volume":"54","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-7424-4663","authenticated-orcid":false,"given":"Masanori","family":"Natsui","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Yasuo","family":"Noguchi","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Mitsuo","family":"Yasuhira","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Hideo","family":"Sato","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Shoji","family":"Ikeda","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9688-8259","authenticated-orcid":false,"given":"Hideo","family":"Ohno","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Tetsuo","family":"Endoh","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4397-8290","authenticated-orcid":false,"given":"Takahiro","family":"Hanyu","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Daisuke","family":"Suzuki","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Akira","family":"Tamakoshi","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Toshinari","family":"Watanabe","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5742-108X","authenticated-orcid":false,"given":"Hiroaki","family":"Honjo","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Hiroki","family":"Koike","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Takashi","family":"Nasuno","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Yitao","family":"Ma","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Takaho","family":"Tanigawa","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1145\/1013235.1013249"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.23919\/VLSIC.2017.8008550"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1063\/1.3672411"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.7567\/JJAP.57.04FN03"},{"key":"ref31","first-page":"108c","article-title":"A 250-MHz 256b-I\/O 1-Mb STT-MRAM with advanced perpendicular MTJ based dual cell for nonvolatile magnetic caches to reduce active power of processors","author":"noguchi","year":"2013","journal-title":"Proc Symp VLSI Technol"},{"key":"ref30","year":"2019","journal-title":"Cortex-M0 Technical Reference Manual Documentation"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2014.6742852"},{"key":"ref36","first-page":"4701","article-title":"More than two orders of magnitude leakage current reduction in look-up table for FPGAs","author":"tran","year":"2005","journal-title":"Proc Int Symp Circuits Syst"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1063\/1.4868332"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.7567\/JJAP.51.04DM02"},{"key":"ref10","first-page":"334","article-title":"An \n$82\\mu$\nA\/MHz microcontroller with embedded FeRAM for energy-harvesting applications","author":"zwerg","year":"2011","journal-title":"Proc IEEE Int Solid-State Circuits Conf"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/ISLPED.2011.5993643"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/2627369.2631641"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2007.894617"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1038\/nmat2804"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TMAG.2013.2251326"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2012.6242460"},{"key":"ref16","first-page":"27.2.1","article-title":"14 ns write speed 128 Mb density embedded STTMRAM with endurance >\n$10^{10}$\n and 10yrs retention@85 &#x00B0;C using novel low damage MTJ integration process","author":"sato","year":"2018","journal-title":"IEDM Tech Dig"},{"key":"ref17","first-page":"202","article-title":"An FPGA-accelerated fully nonvolatile microcontroller unit for sensor-node applications in 40 nm CMOS\/MTJ-hybrid technology achieving 47.14 \n$\\mu$\nW operation at 200 MHz","author":"natsui","year":"2019","journal-title":"Proc IEEE Int Solid-State Circuits Conf"},{"key":"ref18","article-title":"Fundamentals of efficient IoT microcontrollers","author":"myers","year":"2019","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1143\/APEX.2.023004"},{"key":"ref28","first-page":"109","article-title":"A comparative study of STT-MTJ based non-volatile flip-flops","author":"na","year":"2013","journal-title":"Proc IEEE Int Symp Circuits Syst"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2632303"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2013.6571793"},{"key":"ref3","first-page":"388","article-title":"24.1 A 1 Mb Multibit ReRAM computing-in-memory macro with 14.6 ns parallel MAC computing time for CNN based AI edge processors","author":"xue","year":"2019","journal-title":"Proc IEEE Int Solid-State Circuits Conf"},{"key":"ref6","first-page":"86t","article-title":"Sub- \n$\\mu$\nW standby power, \n$< 18~\\mu$\nW\/DMIPS@25MHz MCU with embedded atom-switch programmable logic and ROM","author":"tsuji","year":"2015","journal-title":"Proc Symp VLSI Circuits"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/NANO.2007.4601218"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2016.7417918"},{"key":"ref8","first-page":"184","article-title":"10.5 A 90 nm 20 MHz fully nonvolatile microcontroller for standby-power-critical applications","author":"sakimura","year":"2014","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2016.7573504"},{"key":"ref2","first-page":"494","article-title":"A 65 nm 1 Mb nonvolatile computing-in-memory ReRAM macro with sub-16 ns multiply-and-accumulate for binary DNN AI edge processors","author":"chen","year":"2018","journal-title":"Proc IEEE Int Solid-State Circuits Conf"},{"key":"ref9","first-page":"432","article-title":"An 8 MHz 75 \n$\\mu$\nA\/MHz zero-leakage non-volatile logic-based Cortex-M0 MCU SoC exhibiting 100% digital state retention at V \n$\\rm_{DD}$\n=0V with <400ns wakeup and sleep transitions","author":"bartling","year":"2013","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2018.2799707"},{"key":"ref20","first-page":"106c","article-title":"Fabrication of a 99%-energy-less nonvolatile multi-functional CAM chip using hierarchical power gating for a massively-parallel full-text-search engine","author":"matsunaga","year":"2013","journal-title":"Proc Symp VLSI Technol"},{"key":"ref22","first-page":"194","article-title":"Nonvolatile logic-in-memory array processor in 90nm MTJ\/MOS achieving 75% leakage reduction using cycle-based power gating","author":"natsui","year":"2013","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1587\/elex.10.20130772"},{"key":"ref24","first-page":"172c","article-title":"Fabrication of a 3000-6-input-LUTs embedded and block-level power-gated nonvolatile FPGA chip using p-MTJ-based logic-in-memory structure","author":"suzuki","year":"2015","journal-title":"Proc Symp VLSI Circuits"},{"key":"ref41","first-page":"1","article-title":"Processor with 4.9-\n$\\mu$\ns break-even time in power gating using crystalline In-Ga-Zn-oxide transistor","author":"kobayashi","year":"2013","journal-title":"Proc IEEE Cool Chips XV"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2362853"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2012.6271663"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2016.2574939"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/8880462\/08796413.pdf?arnumber=8796413","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,13]],"date-time":"2022-07-13T21:09:55Z","timestamp":1657746595000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8796413\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,11]]},"references-count":41,"journal-issue":{"issue":"11"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2019.2930910","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2019,11]]}}}