{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,5]],"date-time":"2026-05-05T20:16:59Z","timestamp":1778012219922,"version":"3.51.4"},"reference-count":37,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"12","license":[{"start":{"date-parts":[[2019,12,1]],"date-time":"2019-12-01T00:00:00Z","timestamp":1575158400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,12,1]],"date-time":"2019-12-01T00:00:00Z","timestamp":1575158400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,12,1]],"date-time":"2019-12-01T00:00:00Z","timestamp":1575158400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100004358","name":"Samsung","doi-asserted-by":"publisher","award":["SRFC-IT1702-02"],"award-info":[{"award-number":["SRFC-IT1702-02"]}],"id":[{"id":"10.13039\/100004358","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2019,12]]},"DOI":"10.1109\/jssc.2019.2936765","type":"journal-article","created":{"date-parts":[[2019,9,11]],"date-time":"2019-09-11T19:56:23Z","timestamp":1568231783000},"page":"3466-3477","source":"Crossref","is-referenced-by-count":47,"title":["An Ultra-Low-Jitter, mmW-Band Frequency Synthesizer Based on Digital Subsampling PLL Using Optimally Spaced Voltage Comparators"],"prefix":"10.1109","volume":"54","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-9265-9344","authenticated-orcid":false,"given":"Juyeop","family":"Kim","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-3976-7236","authenticated-orcid":false,"given":"Younghyun","family":"Lim","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2947-6999","authenticated-orcid":false,"given":"Heein","family":"Yoon","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0654-9363","authenticated-orcid":false,"given":"Yongsun","family":"Lee","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-3630-8720","authenticated-orcid":false,"given":"Hangi","family":"Park","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yoonseo","family":"Cho","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3181-2744","authenticated-orcid":false,"given":"Taeho","family":"Seong","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3055-8684","authenticated-orcid":false,"given":"Jaehyouk","family":"Choi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/4.972142"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2014.2305216"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.842851"},{"key":"ref30","first-page":"314","article-title":"A double-tail latch-type voltage sense amplifier with 18 ps setup+hold time","author":"schinkel","year":"2007","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2529004"},{"key":"ref36","first-page":"326","article-title":"A 50-to-66GHz 65 nm CMOS all-digital fractional-N PLL with 220 fsrms jitter","author":"hussein","year":"2017","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2442998"},{"key":"ref34","doi-asserted-by":"crossref","first-page":"614","DOI":"10.1109\/JSSC.2015.2510019","article-title":"A 0.56–2.92 GHz wideband and low phase noise quadrature LO-generator using a single LC-VCO for 2G–4G multistandard cellular transceivers","volume":"51","author":"yoon","year":"2016","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2016.2599516"},{"key":"ref11","first-page":"268","article-title":"Sub-sampling all-digital fractional-N frequency synthesizer with ?111 dBc\/Hz in-band phase noise and an FOM of ?242 dB","author":"chen","year":"2015","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2546304"},{"key":"ref13","first-page":"268","article-title":"A 30 GHz digital sub-sampling fractional-N PLL with 198 fsrms jitter in 65 nm LP CMOS","author":"grimaldi","year":"2019","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2749420"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2177178"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2015.2476295"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TMTT.2016.2647698"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2411623"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2528997"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2403373"},{"key":"ref4","first-page":"112","article-title":"A 100 Gb\/s 1.1 pJ\/b PAM-4 RX with dual-mode 1-tap PAM-4\/3-tap NRZ speculative DFE in 14 nm CMOS FinFET","author":"cevrero","year":"2019","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2013.2273732"},{"key":"ref3","first-page":"378","article-title":"A 7.4-to-14 GHz PLL with 54 fsrms jitter in 16 nm FinFET for integrated RF-data-converter SoCs","author":"turker","year":"2018","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2015816"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2053094"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2032723"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2359670"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2791486"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2820149"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2874013"},{"key":"ref1","year":"2018","journal-title":"E-UTRA Base Station (BS) Radio Transmission and Reception"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2014.2362309"},{"key":"ref22","doi-asserted-by":"crossref","first-page":"821","DOI":"10.1109\/JSSC.2016.2519391","article-title":"A bang bang phase-locked loop using automatic loop gain control and loop latency reduction techniques","volume":"51","author":"kuan","year":"2016","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref21","first-page":"366","article-title":"A ?31 dBc integrated-phase-noise 29 GHz fractional-N frequency synthesizer supporting multiple frequency bands for backward-compatible 5G using a frequency doubler and injection-locked frequency multipliers","author":"yoon","year":"2018","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref24","first-page":"396","article-title":"A ?242 dB FOM and ?75 dBc-reference-spur ring-DCO-based all-digital PLL using a fast phase-error correction technique and a low-power optimal-threshold TDC","author":"seong","year":"2018","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2015.2435691"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TIT.1982.1056489"},{"key":"ref25","first-page":"258","article-title":"A 76 fsrms jitter and ?40 dBc integrated-phase-noise 28-to-31 GHz frequency synthesizer based on digital sub-sampling PLL using optimally spaced voltage comparators and background loop-gain optimization","author":"kim","year":"2019","journal-title":"IEEE ISSCC Dig Tech Papers"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/8910478\/08832221.pdf?arnumber=8832221","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,13]],"date-time":"2022-07-13T21:08:43Z","timestamp":1657746523000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8832221\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,12]]},"references-count":37,"journal-issue":{"issue":"12"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2019.2936765","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2019,12]]}}}