{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,1]],"date-time":"2026-07-01T18:31:40Z","timestamp":1782930700966,"version":"3.54.5"},"reference-count":28,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"11","license":[{"start":{"date-parts":[[2019,11,1]],"date-time":"2019-11-01T00:00:00Z","timestamp":1572566400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,11,1]],"date-time":"2019-11-01T00:00:00Z","timestamp":1572566400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,11,1]],"date-time":"2019-11-01T00:00:00Z","timestamp":1572566400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100002418","name":"Intel Corporation","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100002418","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2019,11]]},"DOI":"10.1109\/jssc.2019.2941259","type":"journal-article","created":{"date-parts":[[2019,10,3]],"date-time":"2019-10-03T19:38:41Z","timestamp":1570131521000},"page":"3149-3160","source":"Crossref","is-referenced-by-count":43,"title":["A 1.6-to-3.0-GHz Fractional-${N}$  MDLL With a Digital-to-Time Converter Range-Reduction Technique Achieving 397-fs Jitter at 2.5-mW Power"],"prefix":"10.1109","volume":"54","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-2301-5702","authenticated-orcid":false,"given":"Alessio","family":"Santiccioli","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0847-9207","authenticated-orcid":false,"given":"Mario","family":"Mercandelli","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0315-514X","authenticated-orcid":false,"given":"Andrea L.","family":"Lacaita","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Carlo","family":"Samori","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0895-1700","authenticated-orcid":false,"given":"Salvatore","family":"Levantino","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2016.7598277"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2941259"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2016.7418040"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2016.7417973"},{"key":"ref14","first-page":"152","article-title":"A 2.5-to-5.75 GHz 5 mW 0.3 psrms-jitter cascaded ring-based digital injection-locked clock multiplier in 65 nm CMOS","author":"coombs","year":"2017","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref15","first-page":"392","article-title":"A 5 GHz 370 fs\n$_{rms}~6.5$\n mW clock multiplier using a crystal-oscillator frequency quadrupler in 65 nm CMOS","author":"megawer","year":"2018","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref16","first-page":"490","article-title":"A 140 fsrms-jitter and ?72 dBc-reference-spur ring-VCO-based injection-locked clock multiplier using a background triple-point frequency\/phase\/slope calibrator","author":"yoo","year":"2019","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref17","first-page":"252","article-title":"A 0.048 mm2 3 mW synthesizable fractional-N PLL with a soft injection-locking technique","author":"deng","year":"2015","journal-title":"ISSCC Dig Tech Papers"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2348311"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2688384"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2018.8310279"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2006225"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2013.2296195"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2002.992946"},{"key":"ref6","first-page":"118","article-title":"A 0.0056 mm2 all-digital MDLL using edge re-extraction, dual-ring VCOs and a 0.3 mW block-sharing frequency tracking loop achieving 292 fsrms Jitter and ?249 dB FOM","author":"yang","year":"2018","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2254552"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2014.6757469"},{"key":"ref7","first-page":"336","article-title":"An all-digital clock generator using a fractionally injection-locked oscillator in 65 nm CMOS","author":"park","year":"2012","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref2","first-page":"58","article-title":"A multiple-crystal interface PLL with VCO realignment to reduce phase noise","author":"ye","year":"2002","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref9","first-page":"326","article-title":"A 0.2-to-1.45 GHz subsampling fractional-N all-digital MDLL with zero-offset aperture PD-based spur cancellation and in-situ timing mismatch detection","author":"kundu","year":"2016","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.876206"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/RFIC.2017.7969029"},{"key":"ref22","first-page":"1","article-title":"A 1.2 ps-jitter fully-synthesizable fully-calibrated fractional-N injection-locked PLL using true arbitrary nonlinearity calibration technique","author":"liu","year":"2018","journal-title":"Proc IEEE Custom Integr Circuits Conf (CICC)"},{"key":"ref21","first-page":"44","article-title":"1.33 mW, 1.6 ps\n$_{rms}$\n-integrated-jitter, 1.8–2.7 GHz ring-oscillator-based fractional-N injection-locked DPLL for Internet-of-things applications","author":"gong","year":"2018","journal-title":"Proc IEEE Radio Freq Integr Circuits Symp (RFIC)"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2008.925948"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1049\/el.2016.4577"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2019.2918027"},{"key":"ref25","doi-asserted-by":"crossref","first-page":"117","DOI":"10.1109\/TCSII.2008.2010189","article-title":"Jitter analysis and a benchmarking figure-of-merit for phase-locked loops","volume":"56","author":"gao","year":"2009","journal-title":"IEEE Trans Circuits Syst II Exp Briefs"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/8880462\/08856254.pdf?arnumber=8856254","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,13]],"date-time":"2022-07-13T21:09:55Z","timestamp":1657746595000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8856254\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,11]]},"references-count":28,"journal-issue":{"issue":"11"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2019.2941259","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2019,11]]}}}