{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,2]],"date-time":"2026-06-02T23:53:51Z","timestamp":1780444431915,"version":"3.54.1"},"reference-count":46,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"2","license":[{"start":{"date-parts":[[2020,2,1]],"date-time":"2020-02-01T00:00:00Z","timestamp":1580515200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,2,1]],"date-time":"2020-02-01T00:00:00Z","timestamp":1580515200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,2,1]],"date-time":"2020-02-01T00:00:00Z","timestamp":1580515200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2020,2]]},"DOI":"10.1109\/jssc.2019.2948008","type":"journal-article","created":{"date-parts":[[2019,10,31]],"date-time":"2019-10-31T21:13:31Z","timestamp":1572556411000},"page":"356-368","source":"Crossref","is-referenced-by-count":31,"title":["A Second-Order Purely VCO-Based CT $\\Delta\\Sigma$  ADC Using a Modified DPLL Structure in 40-nm CMOS"],"prefix":"10.1109","volume":"55","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-9228-5466","authenticated-orcid":false,"given":"Yi","family":"Zhong","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2736-5451","authenticated-orcid":false,"given":"Shaolan","family":"Li","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2181-9042","authenticated-orcid":false,"given":"Xiyuan","family":"Tang","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7933-3673","authenticated-orcid":false,"given":"Linxiao","family":"Shen","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1834-646X","authenticated-orcid":false,"given":"Wenda","family":"Zhao","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7000-7548","authenticated-orcid":false,"given":"Siliang","family":"Wu","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5536-8385","authenticated-orcid":false,"given":"Nan","family":"Sun","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref39","first-page":"926","article-title":"A purely-VCO-based single-loop high-order continuous-time \n$\\Sigma\\Delta$\n ADC","author":"yoon","year":"2014","journal-title":"Proc IEEE Int Symp Circuits Syst (ISCAS)"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.917372"},{"key":"ref33","first-page":"93","article-title":"A second-order purely VCO-based CT \n$\\Delta\\Sigma$\n ADC using a modified DPLL in 40-nm CMOS","author":"zhong","year":"2018","journal-title":"Proc IEEE Asian Solid-State Circuits Conf (A-SSCC)"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/LSSC.2018.2875818"},{"key":"ref31","first-page":"687","article-title":"2nd-order VCO-based CT \n$\\Sigma\\Delta$\n ADC architecture","author":"prathap","year":"2017","journal-title":"Proc IEEE 60th Int Midwest Symp Circuits Syst (MWSCAS)"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1049\/el.2016.1428"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2305651"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2005704"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.910966"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.857417"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2073193"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/82.769775"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2239113"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2293753"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2015.2502166"},{"key":"ref14","first-page":"1","article-title":"A 0.04-mm\n$^{2}~0.9$\n-mW 71-dB SNDR distributed modular \n$\\Delta\\Sigma$\n ADC with VCO-based integrator and digital DAC calibration","author":"yoon","year":"2015","journal-title":"Proc IEEE Custom Integr Circuits Conf (CICC)"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2693244"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.917500"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2032703"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2218062"},{"key":"ref19","first-page":"256c","article-title":"A 54 mw 1.2 GS\/s 71.5 dB SNDR 50 MHz BW VCO-based CT \n$\\Delta\\Sigma$\n ADC using dual phase\/frequency feedback in 65 nm CMOS","author":"reddy","year":"2015","journal-title":"Proc Symp VLSI Circuits (VLSI Circuits)"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2393814"},{"key":"ref4","first-page":"187","article-title":"A 0.2 V \n$0.44~\\mu\\text{W}$\n 20 kHz analog to digital \n$\\Delta\\Sigma$\n modulator with 57 fJ\/conversion FoM","author":"wismar","year":"2006","journal-title":"Proc Eur Solid-State Circuits Conf"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2017.2737830"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/82.775391"},{"key":"ref6","doi-asserted-by":"crossref","first-page":"18","DOI":"10.1109\/TCSI.2009.2018928","article-title":"Analysis and design of voltage-controlled oscillator based analog-to-digital converter","volume":"57","author":"kim","year":"2010","journal-title":"IEEE Trans Circuits Syst I Reg Papers"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2019.2898415"},{"key":"ref5","first-page":"206","article-title":"A 0.2 V, \n$7.5~\\mu\\text{W}$\n, 20 kHz \n$\\Delta\\Sigma$\n modulator with 69 dB SNR in 90 nm CMOS","author":"wismar","year":"2007","journal-title":"Proc Eur Solid-State Circuits Conf"},{"key":"ref8","first-page":"1","article-title":"A 75 dB DR 50 MHz BW \n$3^{rd}$\n-order CT-\n$\\Delta\\Sigma$\n modulator using VCO-based integrators","author":"young","year":"2014","journal-title":"Symp VLSI Circuits Dig Tech Papers"},{"key":"ref7","first-page":"155","article-title":"A 0.02 mm\n$^{2}~65$\n nm CMOS 30 MHz BW all-digital differential VCO-based ADC with 64 dB SNDR","author":"daniels","year":"2010","journal-title":"Proc IEEE Symp VLSI Circuits (VLSIC)"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/82.850418"},{"key":"ref9","first-page":"270","article-title":"A 71 dB SFDR open loop VCO-based ADC using 2-level PWM modulation","author":"rao","year":"2011","journal-title":"Symp VLSI Circuits Dig Tech Papers (VLSIC'12)"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/4.553171"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2007.905648"},{"key":"ref20","first-page":"36c","article-title":"A 0.028 mm\n$^{2}19.8$\n fJ\/step \n$2^{nd}$\n-order VCO-based CT \n$\\Delta\\Sigma$\n modulator using an inherent passive integrator and capacitive feedback in 40 nm CMOS","author":"li","year":"2017","journal-title":"Proc Symp VLSI Circuits"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.820856"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2885554"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2688364"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2017.7993606"},{"key":"ref24","first-page":"328","article-title":"A 5 GS\/s 7.2 ENOB time-interleaved VCO-based ADC achieving 30.5 fJ\/conv-step","author":"baert","year":"2019","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2021086"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2016.7598286"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2006314"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2799938"},{"key":"ref43","doi-asserted-by":"crossref","first-page":"407","DOI":"10.1109\/JSSC.2002.808283","article-title":"Virtual damping and Einstein relation in oscillators","volume":"38","author":"ham","year":"2003","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2018.2837757"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/8972639\/08889451.pdf?arnumber=8889451","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,4,27]],"date-time":"2022-04-27T13:39:31Z","timestamp":1651066771000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8889451\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,2]]},"references-count":46,"journal-issue":{"issue":"2"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2019.2948008","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2020,2]]}}}