{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,15]],"date-time":"2026-07-15T06:35:21Z","timestamp":1784097321284,"version":"3.55.0"},"reference-count":37,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2020,1,1]],"date-time":"2020-01-01T00:00:00Z","timestamp":1577836800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,1,1]],"date-time":"2020-01-01T00:00:00Z","timestamp":1577836800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,1,1]],"date-time":"2020-01-01T00:00:00Z","timestamp":1577836800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100004663","name":"Ministry of Science and Technology, Taiwan","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100004663","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Media Tek"},{"name":"Taiwan Semiconductor Manufacturing Company-Joint Development Program"},{"name":"Taiwan Semiconductor Research Institute"},{"name":"MediaTek-Joint Development Program"},{"name":"M31 Technology Corporation"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2020,1]]},"DOI":"10.1109\/jssc.2019.2952773","type":"journal-article","created":{"date-parts":[[2019,11,27]],"date-time":"2019-11-27T17:29:12Z","timestamp":1574875752000},"page":"189-202","source":"Crossref","is-referenced-by-count":225,"title":["A Twin-8T SRAM Computation-in-Memory Unit-Macro for Multibit CNN-Based AI Edge Processors"],"prefix":"10.1109","volume":"55","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-4993-0087","authenticated-orcid":false,"given":"Xin","family":"Si","sequence":"first","affiliation":[{"name":"Institute of Integrated Circuits and Systems, University of Electronic Science and Technology of China (UESTC), Chengdu, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jia-Jing","family":"Chen","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, National Tsing Hua University (NTHU), Hsinchu, Taiwan"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Yung-Ning","family":"Tu","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, National Tsing Hua University (NTHU), Hsinchu, Taiwan"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Wei-Hsing","family":"Huang","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, National Tsing Hua University (NTHU), Hsinchu, Taiwan"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jing-Hong","family":"Wang","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, National Tsing Hua University (NTHU), Hsinchu, Taiwan"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Yen-Cheng","family":"Chiu","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, National Tsing Hua University (NTHU), Hsinchu, Taiwan"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Wei-Chen","family":"Wei","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, National Tsing Hua University (NTHU), Hsinchu, Taiwan"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Ssu-Yen","family":"Wu","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, National Tsing Hua University (NTHU), Hsinchu, Taiwan"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5337-5680","authenticated-orcid":false,"given":"Xiaoyu","family":"Sun","sequence":"additional","affiliation":[{"name":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-1642-3473","authenticated-orcid":false,"given":"Rui","family":"Liu","sequence":"additional","affiliation":[{"name":"School of Electrical, Computer and Energy Engineering, Arizona State University (ASU), Tempe, AZ, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0068-3652","authenticated-orcid":false,"given":"Shimeng","family":"Yu","sequence":"additional","affiliation":[{"name":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Ren-Shuo","family":"Liu","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, National Tsing Hua University (NTHU), Hsinchu, Taiwan"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4070-5059","authenticated-orcid":false,"given":"Chih-Cheng","family":"Hsieh","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, National Tsing Hua University (NTHU), Hsinchu, Taiwan"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-9689-1236","authenticated-orcid":false,"given":"Kea-Tiong","family":"Tang","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, National Tsing Hua University (NTHU), Hsinchu, Taiwan"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9503-995X","authenticated-orcid":false,"given":"Qiang","family":"Li","sequence":"additional","affiliation":[{"name":"Institute of Integrated Circuits and Systems, University of Electronic Science and Technology of China (UESTC), Chengdu, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6905-6350","authenticated-orcid":false,"given":"Meng-Fan","family":"Chang","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, National Tsing Hua University (NTHU), Hsinchu, Taiwan"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref33","article-title":"Very deep convolutional networks for large-scale image recognition","author":"simonyan","year":"2014","journal-title":"arXiv 1409 1556"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.23919\/VLSIC.2019.8778028"},{"key":"ref31","first-page":"248","article-title":"A ternary based bit scalable, 8.80 TOPS\/W CNN accelerator with many-core processing-in-memory architecture with 896K synapses\/mm2","author":"okumura","year":"2019","journal-title":"Proc Symp VLSI Circuits"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2042254"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2867275"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2880918"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2878830"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2143870"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2778702"},{"key":"ref11","first-page":"10","article-title":"Computing&#x2019;s energy problem (and what we can do about it)","author":"horowitz","year":"2014","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2642198"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2018.8310401"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2018.8310397"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2018.8310398"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2018.8510687"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.23919\/VLSIC.2017.8008465"},{"key":"ref18","article-title":"Xcel-RAM: Accelerating binary neural networks in high-throughput SRAM compute arrays","author":"agrawal","year":"2018","journal-title":"arXiv 1807 00343"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2018.8502421"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2018.8310400"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2017.7870354"},{"key":"ref27","first-page":"314","article-title":"A 28nm 256Kb 6T-SRAM with 280mV Improvement in VMIN Using a Dual-Split-Control Assist Scheme","author":"chang","year":"2015","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2014.220"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2636225"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2016.90"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2016.7418007"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2017.7993626"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2019.2928043"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/MSP.2012.2205597"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/MSSC.2017.2745798"},{"key":"ref1","first-page":"1097","article-title":"ImageNet classification with deep convolutional neural networks","author":"krizhevsky","year":"2012","journal-title":"Proc Adv Neural Inf Process Syst"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2018.2848999"},{"key":"ref22","first-page":"222","article-title":"An always-on \n$3.8~\\mu$\n J\/86% CIFAR-10 mixed-signal binary CNN processor with all memory on chip in 28-nm CMOS","author":"bankman","year":"2018","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref21","doi-asserted-by":"crossref","first-page":"1009","DOI":"10.1109\/JSSC.2016.2515510","article-title":"A 28 nm configurable memory (TCAM\/BCAM\/SRAM) using push-rule 6T bit cell enabling logic-in-memory","volume":"51","author":"jeloka","year":"2016","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref24","first-page":"1","article-title":"Parallelizing SRAM Arrays with Customized Bit-Cell for Binary Neural Networks","author":"liu","year":"2018","journal-title":"Proc 55th ACM\/ESDA\/IEEE Design Automat Conf (DAC)"},{"key":"ref23","first-page":"396","article-title":"24.5 A Twin-8T SRAM computation-in-memory macro for multiple-bit CNN-based machine learning","author":"si","year":"2019","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2015.7298594"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2018.8310262"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/8944135\/08915834.pdf?arnumber=8915834","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,8,23]],"date-time":"2025-08-23T00:58:24Z","timestamp":1755910704000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8915834\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,1]]},"references-count":37,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2019.2952773","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2020,1]]}}}