{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,5]],"date-time":"2026-06-05T05:05:11Z","timestamp":1780635911510,"version":"3.54.1"},"reference-count":39,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"2","license":[{"start":{"date-parts":[[2020,2,1]],"date-time":"2020-02-01T00:00:00Z","timestamp":1580515200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,2,1]],"date-time":"2020-02-01T00:00:00Z","timestamp":1580515200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,2,1]],"date-time":"2020-02-01T00:00:00Z","timestamp":1580515200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2020,2]]},"DOI":"10.1109\/jssc.2019.2952852","type":"journal-article","created":{"date-parts":[[2019,11,27]],"date-time":"2019-11-27T22:29:12Z","timestamp":1574893752000},"page":"426-438","source":"Crossref","is-referenced-by-count":13,"title":["A 951-fs<sub>rms<\/sub> Period Jitter 3.2% Modulation Range in-Band Modulation Spread-Spectrum Clock Generator"],"prefix":"10.1109","volume":"55","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-5838-0075","authenticated-orcid":false,"given":"Hyuk","family":"Sun","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4796-0725","authenticated-orcid":false,"given":"Kazuki","family":"Sobue","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Koichi","family":"Hamashita","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Tejasvi","family":"Anand","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-1948-057X","authenticated-orcid":false,"given":"Un-Ku","family":"Moon","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/4.585289"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.1994.409188"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.813287"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2012.2215792"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/4.568836"},{"key":"ref30","author":"fischette","year":"2009","journal-title":"First Time Every Time-Practical Tips for Phase-Locked Loop Design"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2002.802343"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/4.735535"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1986.1052639"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.1991.164118"},{"key":"ref10","first-page":"162","article-title":"A low-jitter 5000 ppm spread spectrum clock generator for multi-channel SATA transceiver in \n$0.18~\\mu\\text{m}$\n CMOS","author":"lee","year":"2005","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2105690"},{"key":"ref12","first-page":"478","article-title":"A 1.4 psrms-period-jitter TDC-less fractional-N digital PLL with digitally controlled ring oscillator in 65 nm CMOS","author":"grollitsch","year":"2010","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref13","first-page":"70","article-title":"A reconfigurable distributed all-digital clock generator core with SSC and skew correction in 22 nm high-k tri-gate LP CMOS","author":"li","year":"2012","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.857417"},{"key":"ref15","first-page":"352","article-title":"A 56.4-to-63.4 GHz spurious-free all-digital fractional-N PLL in 65 nm CMOS","author":"wu","year":"2013","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2015.7063025"},{"key":"ref17","first-page":"1","article-title":"A 0.951 psrmsperiod jitter, 3.2% modulation range, DSM-free, spread-spectrum PLL","author":"sun","year":"2017","journal-title":"Proc IEEE Custom Integr Circuits Conf"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/5.542410"},{"key":"ref19","author":"lathi","year":"1995","journal-title":"Modern Digital and Analog Communication Systems"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1002\/0471732699"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISEMC.1994.385656"},{"key":"ref27","first-page":"1","article-title":"Tutorial on digital phase-locked loops","author":"perrott","year":"2009","journal-title":"Proc IEEE Custom Integr Circuits Conf"},{"key":"ref3","author":"getz","year":"1996","journal-title":"Understanding and Eliminating EMI in Microcontroller Applications"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.809521"},{"key":"ref29","article-title":"Low phase noise, high bandwidth frequency synthesis techniques","author":"meninger","year":"2005"},{"key":"ref5","first-page":"184","article-title":"Dual-loop spread-spectrum clock generator","author":"li","year":"1999","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref8","first-page":"160","article-title":"Spread-spectrum clock generator for serial ATA using fractional PLL controlled by \n$\\Delta\\Sigma$\n modulator with level shifter","author":"kokubo","year":"2005","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2009.5280788"},{"key":"ref2","author":"tesche","year":"1997","journal-title":"EMC Analysis Methods and Computational Models"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2031577"},{"key":"ref1","author":"anand","year":"0","journal-title":"Wireline Link Performance Survey"},{"key":"ref20","first-page":"71","article-title":"Bi-directional AC coupled interface with adaptive spread spectrum clock generator","author":"komatsu","year":"2007","journal-title":"Proc IEEE Asian Solid-State Circuits Conf"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.820858"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/ISEMC.1995.523633"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.870894"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.908763"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.884829"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2005716"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/8972639\/08915821.pdf?arnumber=8915821","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,4,27]],"date-time":"2022-04-27T13:39:31Z","timestamp":1651066771000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8915821\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,2]]},"references-count":39,"journal-issue":{"issue":"2"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2019.2952852","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2020,2]]}}}