{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,4]],"date-time":"2026-03-04T17:28:11Z","timestamp":1772645291513,"version":"3.50.1"},"reference-count":42,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"3","license":[{"start":{"date-parts":[[2020,3,1]],"date-time":"2020-03-01T00:00:00Z","timestamp":1583020800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,3,1]],"date-time":"2020-03-01T00:00:00Z","timestamp":1583020800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,3,1]],"date-time":"2020-03-01T00:00:00Z","timestamp":1583020800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2020,3]]},"DOI":"10.1109\/jssc.2019.2959487","type":"journal-article","created":{"date-parts":[[2019,12,31]],"date-time":"2019-12-31T21:07:45Z","timestamp":1577826465000},"page":"567-579","source":"Crossref","is-referenced-by-count":9,"title":["An ISI-Resilient Data Encoding for Equalizer-Free Wireline Communication\u2014Dicode Encoding and Error Correction for 24.2-dB Loss With 2.56 pJ\/bit"],"prefix":"10.1109","volume":"55","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-0371-2436","authenticated-orcid":false,"given":"Yusang","family":"Chun","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1737-7950","authenticated-orcid":false,"given":"Tejasvi","family":"Anand","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","first-page":"438","article-title":"A 130 mW 20Gb\/s half-duplex serial link in 28nm CMOS","author":"balan","year":"2014","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2018.8310288"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1137\/0108018"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2012.6330611"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2012.6176875"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2009.2019391"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/TSP.2017.2725221"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2016.2535038"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1002\/j.1538-7305.1950.tb00463.x"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/TIT.2009.2021379"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2317142"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2348556"},{"key":"ref11","first-page":"376","article-title":"A 0.5-to-0.9V, 3-to-16Gb\/s, 1.6-to-3.1pJ\/bit wireline transceiver equalizing 27dB loss at 10Gb\/s with clock domain encoding: Integrated pulse width modulation (iPWM) in 65nm CMOS","author":"ramachandran","year":"2018","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref12","first-page":"488","article-title":"A 16Gb\/s 3.6pJ\/bit wireline transceiver with phase domain equalization scheme: Integrated pulse width modulation (iPWM) in 65nm CMOS","author":"ramachandran","year":"2017","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2018.2879020"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2017.2775619"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2019.8780237"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2003.1221172"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1049\/el:19710089"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TCOM.1972.1091221"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2007.904688"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2001934"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2016.7417906"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/TCE.1963.6373379"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.23919\/VLSIC.2017.8008527"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.874270"},{"key":"ref29","first-page":"480","article-title":"A 32Gb\/s 2.9pJ\/b transceiver for sequence-coded PAM-4 signalling with 4-to-6dB SNR gain in 28nm FDSOI CMOS","author":"aurangozeb","year":"2019","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TADVP.2008.2011366"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.870897"},{"key":"ref7","article-title":"Magnetic storage","author":"thomas","year":"1949","journal-title":"Proc 1st Cambridge Comput Conf"},{"key":"ref2","author":"o\u2019mahony","year":"2019","journal-title":"ISSCC Trends"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2008.4672165"},{"key":"ref1","author":"anand","year":"2019","journal-title":"Wireline Link Performance Survey"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2279057"},{"key":"ref22","first-page":"114","article-title":"A 40-to-56Gb\/s PAM-4 receiver with 10-tap direct decision-feedback equalization in 16nm FinFET","author":"im","year":"2017","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref21","first-page":"230c","article-title":"A 60Gb\/s 173 mW receiver frontend in 65nm CMOS technology","author":"hatamkhani","year":"2015","journal-title":"Proc Symp VLSI Circuits (VLSI Circuits)"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2040117"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/49.87640"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2168871"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.1990.112483"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/GLOCOM.2009.5426027"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2004.1346611"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/9011683\/08946544.pdf?arnumber=8946544","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,4,27]],"date-time":"2022-04-27T13:37:30Z","timestamp":1651066650000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8946544\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,3]]},"references-count":42,"journal-issue":{"issue":"3"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2019.2959487","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2020,3]]}}}