{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,2]],"date-time":"2026-05-02T15:13:13Z","timestamp":1777734793460,"version":"3.51.4"},"reference-count":22,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2020,4,1]],"date-time":"2020-04-01T00:00:00Z","timestamp":1585699200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,4,1]],"date-time":"2020-04-01T00:00:00Z","timestamp":1585699200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,4,1]],"date-time":"2020-04-01T00:00:00Z","timestamp":1585699200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100004368","name":"Taiwan Semiconductor Manufacturing Company","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100004368","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2020,4]]},"DOI":"10.1109\/jssc.2019.2959735","type":"journal-article","created":{"date-parts":[[2020,1,1]],"date-time":"2020-01-01T21:05:44Z","timestamp":1577912744000},"page":"1043-1050","source":"Crossref","is-referenced-by-count":20,"title":["A 7-nm FinFET CMOS PLL With 388-fs Jitter and \u221280-dBc Reference Spur Featuring a Track-and-Hold Charge Pump and Automatic Loop Gain Control"],"prefix":"10.1109","volume":"55","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-5777-4857","authenticated-orcid":false,"given":"Chen-Ting","family":"Ko","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ting-Kuei","family":"Kuan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ruei-Pin","family":"Shen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chih-Hsien","family":"Chang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"crossref","first-page":"117","DOI":"10.1109\/TCSII.2008.2010189","article-title":"Jitter analysis and a benchmarking figure-of-merit for phase-locked loops","volume":"56","author":"gao","year":"2009","journal-title":"IEEE Trans Circuits Syst II Exp Briefs"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2053094"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2015.7231354"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2839038"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2015.2423793"},{"key":"ref15","doi-asserted-by":"crossref","first-page":"821","DOI":"10.1109\/JSSC.2016.2519391","article-title":"A bang bang phase-locked loop using automatic loop gain control and loop latency reduction techniques","volume":"51","author":"kuan","year":"2016","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref16","first-page":"260","article-title":"A 1.22 ps integrated-jitter 0.25-to-4 GHz fractional-N ADPLL in 16 nm FinFET CMOS","author":"tsai","year":"2015","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref17","first-page":"330","article-title":"A 0.17-to-3.5mW 0.15-to-5 GHz SoC PLL with 15 dB build-in supply noise rejection and self-bandwidth control in 14 nm CMOS","author":"shen","year":"2016","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref18","first-page":"328","article-title":"A 0.0049mm2 2.3GHz sub-sampling ringoscillator PLL with time-based loop filter achieving ?236.2dB jitter-FOM","author":"chuang","year":"2017","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref19","first-page":"178","article-title":"A 0.5V 1.6 mW 2.4 GHz fractional-N all-digital PLL for Bluetooth LE with PVT-insensitive TDC using switched-capacitor doubler in 28 nm CMOS","author":"kuo","year":"2017","journal-title":"IEEE Symp VLSI Circuits Tech Dig"},{"key":"ref4","first-page":"114","article-title":"Analog\/RF wonderland: Circuit and technology co-optimization in advanced finFET technology","author":"hsueh","year":"2016","journal-title":"Symp VLSI Technol Tech Dig"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.7567\/SSDM.2009.E-3-2L"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2013.6724597"},{"key":"ref5","article-title":"Design and technology co-optimization for mobile SoCs","author":"terzioglu","year":"2015","journal-title":"Proc Int Conf IC Design Technol"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2359670"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2032723"},{"key":"ref2","first-page":"110t","article-title":"Enabling circuit design using FinFETs through close ecosystem collaboration","author":"sheu","year":"2013","journal-title":"Proc Symp VLSI Tech"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2018.8357060"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2546304"},{"key":"ref20","first-page":"268","article-title":"A sub-sampling all-digital fractional-N frequency synthesizer with–111 dBc\/Hz in-band phase noise and an FOM of–242 dB","author":"chen","year":"2015","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2596770"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/JMEMS.2006.883569"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/9048008\/08948001.pdf?arnumber=8948001","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,4,27]],"date-time":"2022-04-27T13:36:16Z","timestamp":1651066576000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8948001\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,4]]},"references-count":22,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2019.2959735","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2020,4]]}}}