{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,9]],"date-time":"2026-01-09T21:55:09Z","timestamp":1767995709744,"version":"3.49.0"},"reference-count":23,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2020,4,1]],"date-time":"2020-04-01T00:00:00Z","timestamp":1585699200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,4,1]],"date-time":"2020-04-01T00:00:00Z","timestamp":1585699200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,4,1]],"date-time":"2020-04-01T00:00:00Z","timestamp":1585699200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100000185","name":"Defense Advanced Research Projects Agency","doi-asserted-by":"publisher","award":["D16AP00122"],"award-info":[{"award-number":["D16AP00122"]}],"id":[{"id":"10.13039\/100000185","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2020,4]]},"DOI":"10.1109\/jssc.2019.2963005","type":"journal-article","created":{"date-parts":[[2020,1,14]],"date-time":"2020-01-14T22:54:48Z","timestamp":1579042488000},"page":"908-919","source":"Crossref","is-referenced-by-count":22,"title":["Liquid Silicon: A Nonvolatile Fully Programmable Processing-in-Memory Processor With Monolithically Integrated ReRAM"],"prefix":"10.1109","volume":"55","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-1111-7178","authenticated-orcid":false,"given":"Yue","family":"Zha","sequence":"first","affiliation":[]},{"given":"Etienne","family":"Nowak","sequence":"additional","affiliation":[]},{"given":"Jing","family":"Li","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","first-page":"84","article-title":"A 65 nm ReRAM-enabled nonvolatile processor with \n$6\\times$\n reduction in restore time and \n$4\\times$\n higher clock frequency using adaptive data retention and self-write-termination nonvoltile logic","author":"liu","year":"2016","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref11","first-page":"172c","article-title":"Fabrication of a 3000–6-input-LUTs embedded and block-level power-gated nonvolatile FPGA chip using p-MTJ-based logic-in-memory structure","author":"suzuki","year":"2015","journal-title":"Proc Symp VLSI Circuits (VLSI Circuits)"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2012.6177067"},{"key":"ref13","first-page":"265","article-title":"Tensorflow, A system for large-scale machine learning","author":"abadi","year":"2016","journal-title":"Proceedings of Operating System Design and Implementation"},{"key":"ref14","first-page":"120","article-title":"Reconfigurable in-memory computing with resistive memory crossbar","author":"zha","year":"2016","journal-title":"Proc 35th Int Conf Comput Aided Design (ICCAD)"},{"key":"ref15","first-page":"129","article-title":"A 6.8 TOPS\/W energy efficiency, \n$1.5~\\mu\\text{W}$\n power consumption, pulse width modulation neuromorphic circuits for near–data computing with SSD","author":"tsurumi","year":"2018","journal-title":"Proc IEEE Asian Solid-State Circuits Conf (A-SSCC)"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/1807167.1807209"},{"key":"ref17","first-page":"51","article-title":"Liquid Silicon: A data–centric reconfigurable architecture enabled by RRAM technology","author":"zha","year":"2018","journal-title":"Proc ACM Int Symp Field-Program Gate Arrays (FPGA)"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2019.2894387"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/3173162.3173167"},{"key":"ref4","first-page":"37","article-title":"An ultra–high energy–efficient reconfigurable processor for deep neural networks with binary\/ternary weights in 28 NM CMOS","author":"yin","year":"2018","journal-title":"Proc IEEE Symp VLSI Circuits"},{"key":"ref3","first-page":"496","article-title":"A 65 nm 4 Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3 ns and 55.8TOPS\/W fully parallel product-sum operation for binary DNN edge processors","author":"khwa","year":"2018","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref6","first-page":"260t","article-title":"A 462GOPs\/J RRAM-based nonvolatile intelligent processor for energy harvesting IoE system featuring nonvolatile logics and processing-in-memory","author":"su","year":"2017","journal-title":"Proc Symp VLSI Technol"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.23919\/VLSIC.2017.8008533"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2016.7838348"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2292055"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2018.8502309"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2018.8357071"},{"key":"ref9","article-title":"Logic synthesis and optimization benchmarks user guide: Version 3.0","author":"yang","year":"1991"},{"key":"ref20","first-page":"my-7","article-title":"Data retention statistics and modelling in HfO2 resistive switching memories","author":"ambrogio","year":"2015","journal-title":"Proc IEEE Int Rel Phys Symp"},{"key":"ref22","doi-asserted-by":"crossref","first-page":"7:1","DOI":"10.1147\/JRD.2014.2380198","article-title":"CAPI: A coherent accelerator processor interface","volume":"59","author":"stuecheli","year":"2015","journal-title":"IBM J Res Develop"},{"key":"ref21","year":"2009","journal-title":"An Introduction to the Intel QuickPath Interconnect"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/LCA.2014.2333735"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/9048008\/08957229.pdf?arnumber=8957229","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,4,27]],"date-time":"2022-04-27T13:36:16Z","timestamp":1651066576000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8957229\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,4]]},"references-count":23,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2019.2963005","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2020,4]]}}}