{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,30]],"date-time":"2026-01-30T02:40:02Z","timestamp":1769740802922,"version":"3.49.0"},"reference-count":65,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2020,4,1]],"date-time":"2020-04-01T00:00:00Z","timestamp":1585699200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,4,1]],"date-time":"2020-04-01T00:00:00Z","timestamp":1585699200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,4,1]],"date-time":"2020-04-01T00:00:00Z","timestamp":1585699200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"name":"Global Foundries"},{"name":"Intel Labs"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2020,4]]},"DOI":"10.1109\/jssc.2019.2963589","type":"journal-article","created":{"date-parts":[[2020,1,14]],"date-time":"2020-01-14T21:16:17Z","timestamp":1579036577000},"page":"1064-1076","source":"Crossref","is-referenced-by-count":20,"title":["Sub-Sampling Direct RF-to-Digital Converter With 1024-APSK Modulation for High Throughput Polar Receiver"],"prefix":"10.1109","volume":"55","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-8437-7726","authenticated-orcid":false,"given":"Hechen","family":"Wang","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0003-1691-6649","authenticated-orcid":false,"given":"Fa Foster","family":"Dai","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0506-7621","authenticated-orcid":false,"given":"Zhan","family":"Su","sequence":"additional","affiliation":[]},{"given":"Yanjie","family":"Wang","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/MWSYM.2013.6697758"},{"key":"ref38","article-title":"A 25&#x2013;102 GHz 2.81-5.64 mW tunable divide-by-4 in 28 nm CMOS","author":"vigilante","year":"2015","journal-title":"Proc IEEE A-SSCC"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2015.7063035"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2647941"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2464708"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2362843"},{"key":"ref37","doi-asserted-by":"crossref","first-page":"357","DOI":"10.1109\/JSSC.2015.2492781","article-title":"A 2.02-5.16 fJ\/conversion step 10 bit hybrid coarse-fine SAR ADC with time-domain quantizer in 90 nm CMOS","volume":"51","author":"chen","year":"2016","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref36","first-page":"143","article-title":"A 14-Bit, 1-ps resolution, two-step ring and 2D Vernier TDC in 130 nm CMOS technology","author":"wang","year":"2017","journal-title":"Proc IEEE ESSCIRC"},{"key":"ref35","first-page":"336","article-title":"A 65 nm CMOS ADPLL with 360 \n$\\mu\\text{W}$\n 1.6ps-INL SS-ADC-based period-detection-free TDC","author":"sai","year":"2016","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref34","article-title":"A 330 \n$\\mu\\text{W}$\n 1.25ps 400fs-INL Vernier time-to-digital converter with 2D reconfigurable spiral arbiter array and \n$2^{nd}$\n-order \n$\\Delta\\Sigma$\n linearization","author":"wang","year":"2017","journal-title":"Proc IEEE CICC"},{"key":"ref60","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2017.7870466"},{"key":"ref62","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2774280"},{"key":"ref61","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2019.8702299"},{"key":"ref63","doi-asserted-by":"crossref","first-page":"1429","DOI":"10.1109\/JSSC.2013.2252516","article-title":"A 6-b 4.1-GS\/s flash ADC with time-domain latch interpolation in 90-nm CMOS","volume":"48","author":"kim","year":"2013","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2216651"},{"key":"ref64","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2303791"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/IEEESTD.2017.8066476"},{"key":"ref65","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2704595"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2253411"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2472599"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2017.7870299"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2013.2284172"},{"key":"ref22","article-title":"Radio frequency (RF) to digital polar data converter and time-to-digital converter based time domain signal processing receiver","author":"dai","year":"2019"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.23919\/VLSIC.2019.8778052"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2654322"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2016.2564680"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/IEEESTD.2016.7524656"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2017.2765312"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2014709"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2047435"},{"key":"ref59","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2591822"},{"key":"ref58","article-title":"A 280MS\/s 12b SAR-assisted hybrid ADC with time domain sub-range quantizer in 45 nm CMOS","author":"su","year":"2019","journal-title":"Proc IEEE CICC"},{"key":"ref57","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2747128"},{"key":"ref56","article-title":"Vernier ring time-to-digital converter based digital phase locked loop","author":"yu","year":"2011"},{"key":"ref55","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2297412"},{"key":"ref54","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2788872"},{"key":"ref53","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2399673"},{"key":"ref52","first-page":"1","article-title":"A 0.84ps-LSB 2.47 mW time-to-digital converter using charge pump and SAR-ADC","author":"xu","year":"2013","journal-title":"Proc IEEE CICC"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2217854"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/RFIC.2016.7508269"},{"key":"ref40","first-page":"392","article-title":"A 2.2 GHz 7.6 mW sub-sampling PLL with -126dBc\/Hz in-band phase noise and 0.15psrms jitter in 0.18 \n$\\mu\\text{m}$\n CMOS","author":"gao","year":"2009","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2281142"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2413846"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2672979"},{"key":"ref15","doi-asserted-by":"crossref","first-page":"598","DOI":"10.1109\/JSSC.2015.2508023","article-title":"A broadband mixed-signal CMOS power amplifier with a hybrid class-G Doherty efficiency enhancement technique","volume":"51","author":"hu","year":"2016","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2358554"},{"key":"ref17","first-page":"218","article-title":"A digital multimode polar transmitter supporting 40 MHz LTE carrier aggregation in 28 nm CMOS","author":"fulde","year":"2017","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2544784"},{"key":"ref19","first-page":"348","article-title":"A 6x-oversampling 10GS\/s 60GHz polar transmitter with 15.3% average PA efficiency in 40 nm CMOS","author":"khalaf","year":"2015","journal-title":"Proc Conf 41st Eur Solid-State Circuits Conf (ESSCIRC)"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TMTT.2014.2307876"},{"key":"ref3","doi-asserted-by":"crossref","first-page":"845","DOI":"10.1109\/JSSC.2015.2511164","article-title":"A 2.7 mW\/channel 48&#x2013;1000 MHz direct sampling full-band cable receiver","volume":"51","author":"wu","year":"2016","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref6","article-title":"A modular 16 nm direct&#x2013;RF TX\/RX embedding 9GS\/S DAC and 4.5GS\/S ADC with 90 dB isolation and sub&#x2013;80PS channel alignment for monolithic integration in 5G base&#x2013;station SoC","author":"erdmann","year":"2018","journal-title":"IEEE Int Symp VLSI Circuits Dig"},{"key":"ref5","article-title":"A bidirectional lens-free digital-bits-in\/-out 0.57 mm2 Terahertz nano-radio in CMOS with 49.3 mW peak power consumption supporting 50 cm Internet-of-Things communication","author":"chi","year":"2017","journal-title":"Proc IEEE Custom Integr Circuits Conf (CICC)"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2747758"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2019.2903650"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1109\/4.823449"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2019.8780339"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2880186"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2557807"},{"key":"ref48","first-page":"230","article-title":"A 24 dBm 2-to-4.3 GHz wideband digital power amplifier with built-in AM-PM distortion self-compensation","author":"park","year":"2017","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2582899"},{"key":"ref42","first-page":"1","article-title":"A 28 nm CMOS digital fractional-N PLL with -245.5 dB FOM and a frequency tripler for 802.11abgn\/ac radio","author":"gao","year":"2015","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2638882"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2682841"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.857417"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/9048008\/08959379.pdf?arnumber=8959379","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,4,27]],"date-time":"2022-04-27T13:35:53Z","timestamp":1651066553000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8959379\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,4]]},"references-count":65,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2019.2963589","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2020,4]]}}}