{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,14]],"date-time":"2026-04-14T16:20:45Z","timestamp":1776183645982,"version":"3.50.1"},"reference-count":67,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","license":[{"start":{"date-parts":[[2020,1,1]],"date-time":"2020-01-01T00:00:00Z","timestamp":1577836800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,1,1]],"date-time":"2020-01-01T00:00:00Z","timestamp":1577836800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,1,1]],"date-time":"2020-01-01T00:00:00Z","timestamp":1577836800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"name":"Research and Development Program in Key Areas of Guangdong Province","award":["2019B010116002"],"award-info":[{"award-number":["2019B010116002"]}]},{"name":"Innovation and Technology Fund ITF of Hong Kong","award":["GHP\/004\/18SZ"],"award-info":[{"award-number":["GHP\/004\/18SZ"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2020]]},"DOI":"10.1109\/jssc.2020.2967562","type":"journal-article","created":{"date-parts":[[2020,1,30]],"date-time":"2020-01-30T21:42:07Z","timestamp":1580420527000},"page":"1-19","source":"Crossref","is-referenced-by-count":66,"title":["A 0.65-V 12-16-GHz Sub-Sampling PLL With 56.4-fsrms Integrated Jitter and -256.4-dB FoM"],"prefix":"10.1109","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-9009-9045","authenticated-orcid":false,"given":"Zhao","family":"Zhang","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9970-4988","authenticated-orcid":false,"given":"Guang","family":"Zhu","sequence":"additional","affiliation":[]},{"given":"C. Patrick","family":"Yue","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref39","first-page":"258","article-title":"A 76 fs\n$_{\\mathrm {rms}}$\n Jitter and ?40 dBc integrated-phase-noise 28-to-31 GHz frequency synthesizer based on digital sub-sampling PLL using optimally spaced voltage comparators and background loop-gain optimization","author":"kim","year":"2019","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/TMTT.2018.2840987"},{"key":"ref33","first-page":"270","article-title":"A 25.4-to-29.5 GHz 10.2 mW isolated sub-sampling PLL achieving ?252.9 dB jitter-power FoM and ?63 dBc reference spur","author":"yang","year":"2019","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2018.8502425"},{"key":"ref31","first-page":"182","article-title":"A 164 fs\n$_{\\mathrm {rms}}~9$\n-to-18 GHz sampling phase detector based PLL with in-band noise suppression and robust frequency acquisition in 16 nm FinFET","author":"raj","year":"2017","journal-title":"Symp VLSI Circuits Dig Tech Papers"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2539344"},{"key":"ref37","first-page":"440","article-title":"A 2.2 GHz ?242 dB-FOM 4.2 mW ADC-PLL using digital sub-sampling architecture","author":"siriburanon","year":"2015","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref36","first-page":"256","article-title":"A sub-sampling all-digital fractional-n frequency synthesizer with ?111 dBc\/Hz in-band phase noise and an FOM of ?242 dB","author":"chen","year":"2015","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref35","first-page":"1","article-title":"A 0.008 mm2 2.4 GHz type-I sub-sampling ring-oscillator-based phase-locked loop with a ?239.7 dB FoM and ?64 dBc reference spurs","author":"nagam","year":"2018","journal-title":"Proc IEEE Custom Integr Circuits Conf (CICC)"},{"key":"ref34","first-page":"256","article-title":"A 0.01 mm2 4.6-to-5.6 GHz sub-sampling type-I frequency synthesizer with ?254 dB FOM","author":"sharkia","year":"2018","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref60","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.857417"},{"key":"ref62","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2011.2124510"},{"key":"ref61","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.826338"},{"key":"ref63","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2017.2679683"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2442998"},{"key":"ref64","first-page":"268","article-title":"A 30 GHz digital sub-sampling fractional-N PLL with 198 fs\n$_{\\mathrm {rms}}$\n jitter in 65 nm LP CMOS","author":"grimaldi","year":"2019","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2403373"},{"key":"ref65","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2013.2268514"},{"key":"ref66","article-title":"Theory and implementation of digital bang-bang frequency synthesizers for high speed serial data communications","author":"da dalt","year":"2007"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2596766"},{"key":"ref67","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2217854"},{"key":"ref2","first-page":"132","article-title":"A 28 nm 0.6 V low-power DSP for mobile applications","author":"gammie","year":"2016","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref1","first-page":"312","article-title":"Computationally enable total energy minimization under performance requirement for a voltage-regulated 0.38-to-0.58 V microprocessor in 65 nm CMOS","author":"rahman","year":"2019","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2015.2411791"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2810184"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2574804"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2032723"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2883090"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2053094"},{"key":"ref25","first-page":"139","article-title":"A 2.9&#x2013;4.0-GHz fractional-N digital PLL with bang-bang phase detector and 560-fs\n$_{\\mathrm {rms}}$\n Integrated Jitter at 4.5-mW power","author":"gao","year":"2010","journal-title":"Symp VLSI Circuits Dig Tech Papers"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2143950"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2016.2619362"},{"key":"ref59","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2598768"},{"key":"ref58","doi-asserted-by":"crossref","first-page":"117","DOI":"10.1109\/TCSII.2008.2010189","article-title":"Jitter analysis and a benchmarking figure-of-merit for phase-locked loops","volume":"56","author":"gao","year":"2009","journal-title":"IEEE Trans Circuits Syst II Exp Briefs"},{"key":"ref57","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2014.2345296"},{"key":"ref56","doi-asserted-by":"crossref","first-page":"2908","DOI":"10.1109\/TCSI.2015.2486078","article-title":"A new PVT compensation technique based on current comparison for low-voltage, near sub-threshold LNA","volume":"62","author":"vinaya","year":"2015","journal-title":"IEEE Trans Circuits Syst I Reg Papers"},{"key":"ref55","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2239114"},{"key":"ref54","doi-asserted-by":"crossref","first-page":"626","DOI":"10.1109\/JSSC.2015.2511157","article-title":"A 2.4 GHz 4 mW integer-N inductorless RF synthesizer","volume":"51","author":"kong","year":"2016","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref53","first-page":"508","article-title":"A 10 GHz low-power multi-modulus frequency divider using extended true single-phase clock (E-TSPC) logic","author":"jung","year":"2012","journal-title":"Proc IEEE Eur Microw Integr Circuit Conf"},{"key":"ref52","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2014.6942114"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ASSCC.2014.7008936"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2019.8662322"},{"key":"ref40","first-page":"258","article-title":"A dividerless reference-sampling RF PLL with ?253.5 dB jitter FOM and-67 dBc reference spurs","author":"sharma","year":"2018","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref12","first-page":"378","article-title":"A 7.4-to-14 GHz PLL with 54 fs\n$_{\\mathrm {rms}}$\n jitter in 16 nm FinFET for integrated RF-data-converter SoCs","author":"turker","year":"2018","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref13","first-page":"160c","article-title":"A 288 fs RMS jitter versatile 8&#x2013;12.4 GHz wide-band fractional-N synthesizer for SONET and SerDes communication standards in 40 nm CMOS","author":"ahmadi","year":"2013","journal-title":"Symp VLSI Circuits Dig Tech Papers"},{"key":"ref14","first-page":"264","article-title":"A fractional-N synthesizer with 110 fs\n$_{\\mathrm {rms}}$\n jitter and a reference quadrupler for wideband 802.11ax","author":"song","year":"2019","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref15","first-page":"192c","article-title":"An 8.5 mW, 0.07 mm2 ADPLL in 28 nm CMOS with sub-ps resolution TDC and < 230 fs RMS jitter","author":"shen","year":"2013","journal-title":"Symp VLSI Circuits Dig Tech Papers"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2638882"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2946134"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2019.2911531"},{"key":"ref19","doi-asserted-by":"crossref","first-page":"1033","DOI":"10.1109\/TCSII.2015.2455292","article-title":"A subharmonically injection-locked all-digital PLL without main divider","volume":"62","author":"wei","year":"2015","journal-title":"IEEE Trans Circuits Syst II Exp Briefs"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2786716"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2015.2395634"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2018.2797280"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/RFIC.2015.7337766"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2843337"},{"key":"ref7","first-page":"183","article-title":"A 0.2 GHz to 4 GHz hybrid PLL (ADPLL\/charge-pump-PLL) in 7 nm FinFET CMOS featuring 0.619 PS integrated jitter and 0.6 US settling time at 2.3 mW","author":"tsai","year":"2018","journal-title":"Symp VLSI Circuits Dig Tech Papers"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2227603"},{"key":"ref9","first-page":"330","article-title":"A 0.17-to-3.5 mW 0.15-to-5 GHz SoC PLL with 15 dB built-in supply noise rejection and self-bandwidth control in 14 nm CMOS","author":"shen","year":"2016","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2280409"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2011.2158752"},{"key":"ref48","first-page":"332","article-title":"A 0.2 V trifilar-coil DCO with DC-DC converter in 16 nm FinFET CMOS with 188 dB FOM, 1.3 kHz resolution, and frequency pushing of 38 MHz\/V for energy harvesting applications","author":"li","year":"2017","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref47","first-page":"335","article-title":"A Class-D CMOS DCO with an on-chip LDO","author":"fanori","year":"2017","journal-title":"Proc Eur Solid-State Circuits Conf (ESSCIRC)"},{"key":"ref42","first-page":"488","article-title":"A 0.65 V 12-to-16 GHz sub-sampling PLL with 56.4 fs\n$_{rms}$\n integrated jitter and ?256.4 dB FoM","author":"zhang","year":"2019","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2597847"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2018.2858197"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2015.2407753"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/4359912\/08976116.pdf?arnumber=8976116","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,4,27]],"date-time":"2022-04-27T13:37:31Z","timestamp":1651066651000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8976116\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020]]},"references-count":67,"URL":"https:\/\/doi.org\/10.1109\/jssc.2020.2967562","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2020]]}}}