{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,15]],"date-time":"2026-04-15T20:31:35Z","timestamp":1776285095960,"version":"3.50.1"},"reference-count":35,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"9","license":[{"start":{"date-parts":[[2020,9,1]],"date-time":"2020-09-01T00:00:00Z","timestamp":1598918400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,9,1]],"date-time":"2020-09-01T00:00:00Z","timestamp":1598918400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,9,1]],"date-time":"2020-09-01T00:00:00Z","timestamp":1598918400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2020,9]]},"DOI":"10.1109\/jssc.2020.2987714","type":"journal-article","created":{"date-parts":[[2020,4,29]],"date-time":"2020-04-29T21:10:21Z","timestamp":1588194621000},"page":"2609-2621","source":"Crossref","is-referenced-by-count":193,"title":["A Programmable Heterogeneous Microprocessor Based on Bit-Scalable In-Memory Computing"],"prefix":"10.1109","volume":"55","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-8692-1860","authenticated-orcid":false,"given":"Hongyang","family":"Jia","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0218-9906","authenticated-orcid":false,"given":"Hossein","family":"Valavi","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6667-1833","authenticated-orcid":false,"given":"Yinqi","family":"Tang","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6909-0612","authenticated-orcid":false,"given":"Jintao","family":"Zhang","sequence":"additional","affiliation":[]},{"given":"Naveen","family":"Verma","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2018.8510687"},{"key":"ref32","first-page":"496","article-title":"A 65 nm 4 Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3 ns and 55.8 TOPS\/W fully parallel product-sum operation for binary DNN edge processors","author":"khwa","year":"2018","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2778702"},{"key":"ref30","first-page":"246","article-title":"14.5 envision: A 0.26-to-10 TOPS\/W subword-parallel dynamic-voltage-accuracy-frequency-scalable convolutional neural network processor in 28 nm FDSOI","author":"moons","year":"2017","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref35","first-page":"120c","article-title":"A 5.1pJ\/Neuron 127.3 $\\mu\\text{s}$\n\/inference RNN-based speech recognition processor using 16 computing-in-memory SRAM macros in 65 nm CMOS","author":"guo","year":"2019","journal-title":"Proc Symp VLSI Circuits"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2952773"},{"key":"ref10","first-page":"10","article-title":"1.1 Computing’s energy problem (and what we can do about it)","author":"horowitz","year":"2014","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2017.2761740"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/HOTCHIPS.2019.8875632"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/MSSC.2019.2922889"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2939682"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2018.00015"},{"key":"ref16","first-page":"490","article-title":"A 42 pJ\/decision 3.12 TOPS\/W robust in-memory machine learning classifier with on-chip training","author":"gonugondla","year":"2018","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2642198"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2019.2912352"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ICASSP.2019.8683521"},{"key":"ref28","first-page":"6869","article-title":"Quantized neural networks: Training neural networks with low precision weights and activations","volume":"18","author":"hubara","year":"2017","journal-title":"J Mach Learn Res"},{"key":"ref4","article-title":"Very deep convolutional networks for large-scale image recognition","author":"simonyan","year":"2014","journal-title":"arXiv 1409 1556"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001139"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2016.91"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2616357"},{"key":"ref29","article-title":"PACT: Parameterized clipping activation for quantized neural networks","author":"choi","year":"2018","journal-title":"arXiv 1805 06085"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1162\/neco.1997.9.8.1735"},{"key":"ref8","article-title":"Deep compression: Compressing deep neural networks with pruning, trained quantization and Huffman coding","author":"han","year":"2015","journal-title":"arXiv 1510 00149 [cs]"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001163"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2016.90"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2019.2954495"},{"key":"ref1","first-page":"1097","article-title":"ImageNet classification with deep convolutional neural networks","author":"krizhevsky","year":"2012","journal-title":"Proc Adv Neural Inf Process Syst"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2899730"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/LSSC.2019.2902738"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2869150"},{"key":"ref24","article-title":"BERT: Pre-training of deep bidirectional transformers for language understanding","author":"devlin","year":"2018","journal-title":"arXiv 1810 04805"},{"key":"ref23","first-page":"173","article-title":"Deep speech 2: End-to-end speech recognition in English and Mandarin","volume":"48","author":"amodei","year":"2016","journal-title":"Proc Int Conf Mach Learn (ICML)"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2016.2537824"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/PATMOS.2017.8106976"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/9177374\/09082159.pdf?arnumber=9082159","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,4,27]],"date-time":"2022-04-27T13:38:22Z","timestamp":1651066702000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9082159\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,9]]},"references-count":35,"journal-issue":{"issue":"9"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2020.2987714","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2020,9]]}}}