{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,1]],"date-time":"2026-06-01T23:39:24Z","timestamp":1780357164813,"version":"3.54.1"},"reference-count":19,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"9","license":[{"start":{"date-parts":[[2020,9,1]],"date-time":"2020-09-01T00:00:00Z","timestamp":1598918400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,9,1]],"date-time":"2020-09-01T00:00:00Z","timestamp":1598918400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,9,1]],"date-time":"2020-09-01T00:00:00Z","timestamp":1598918400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100004663","name":"Ministry of Science and Technology (MOST) of Taiwan","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100004663","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2020,9]]},"DOI":"10.1109\/jssc.2020.2993672","type":"journal-article","created":{"date-parts":[[2020,5,21]],"date-time":"2020-05-21T21:29:50Z","timestamp":1590096590000},"page":"2478-2488","source":"Crossref","is-referenced-by-count":30,"title":["A 0.07-mm<sup>2<\/sup> 162-mW DAC Achieving &gt;65 dBc SFDR and &lt; \u221270 dBc IM3 at 10 GS\/s With Output Impedance Compensation and Concentric Parallelogram Routing"],"prefix":"10.1109","volume":"55","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-1465-9995","authenticated-orcid":false,"given":"Hung-Yi","family":"Huang","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5477-0583","authenticated-orcid":false,"given":"Tai-Haur","family":"Kuo","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/4.808896"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/82.850417"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2003.821307"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2006.882355"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2168651"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2126410"},{"key":"ref16","first-page":"360","article-title":"A 16 b 6 GS\/s Nyquist DAC with IMD < ?90dBc up to 1.9 GHz in 16 nm CMOS","author":"lin","year":"2018","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2164302"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2871143"},{"key":"ref19","first-page":"250","article-title":"A 1.5 V 200 MS\/s 13b 25 mW DAC with randomized nested background calibration in $0.13~\\mu\\text{m}$\n CMOS","author":"clara","year":"2007","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2301769"},{"key":"ref3","first-page":"280","article-title":"16.3 A 330 mW 14b 6.8 GS\/s dual-mode RF DAC in 16 nm FinFET achieving ?70.8 dBc ACPR in a 20 MHz channel at 5.2 GHz","author":"erdmann","year":"2017","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2032624"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2003.1205700"},{"key":"ref8","first-page":"136c","article-title":"A 0.07 mm2 210 mW single-1.1 V-supply 14-bit 10 GS\/s DAC with concentric parallelogram routing and output impedance compensation","author":"huang","year":"2019","journal-title":"Proc IEEE Symp VLSI Circuits (VLSIC)"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2010.2052491"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2749441"},{"key":"ref1","first-page":"1","article-title":"A 14-bit 8.9 GS\/s RF DAC in 40 nm CMOS achieving >71dBc LTE ACPR at 2.9 GHz","author":"ravinuthula","year":"2016","journal-title":"Proc IEEE Symp VLSI Circuits (VLSIC)"},{"key":"ref9","first-page":"58","article-title":"3.4 A 36 Gb\/s PAM4 transmitter using an 8b 18 GS\/S DAC in 28 nm CMOS","author":"nazemi","year":"2015","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/9177374\/09098055.pdf?arnumber=9098055","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,4,27]],"date-time":"2022-04-27T13:38:22Z","timestamp":1651066702000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9098055\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,9]]},"references-count":19,"journal-issue":{"issue":"9"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2020.2993672","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2020,9]]}}}