{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,19]],"date-time":"2026-02-19T16:16:09Z","timestamp":1771517769007,"version":"3.50.1"},"reference-count":19,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2021,1,1]],"date-time":"2021-01-01T00:00:00Z","timestamp":1609459200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,1,1]],"date-time":"2021-01-01T00:00:00Z","timestamp":1609459200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,1,1]],"date-time":"2021-01-01T00:00:00Z","timestamp":1609459200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2021,1]]},"DOI":"10.1109\/jssc.2020.3017775","type":"journal-article","created":{"date-parts":[[2020,9,2]],"date-time":"2020-09-02T20:31:37Z","timestamp":1599078697000},"page":"212-224","source":"Crossref","is-referenced-by-count":13,"title":["An 8.5-Gb\/s\/Pin 12-Gb LPDDR5 SDRAM With a Hybrid-Bank Architecture, Low Power, and Speed-Boosting Techniques"],"prefix":"10.1109","volume":"56","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-6990-5869","authenticated-orcid":false,"given":"Chang-Kyo","family":"Lee","sequence":"first","affiliation":[]},{"given":"Hyung-Joon","family":"Chi","sequence":"additional","affiliation":[]},{"given":"Jin-Seok","family":"Heo","sequence":"additional","affiliation":[]},{"given":"Jung-Hwan","family":"Park","sequence":"additional","affiliation":[]},{"given":"Jin-Hun","family":"Jang","sequence":"additional","affiliation":[]},{"given":"Dongkeon","family":"Lee","sequence":"additional","affiliation":[]},{"given":"Jae-Hoon","family":"Jung","sequence":"additional","affiliation":[]},{"given":"Dong-Hun","family":"Lee","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0801-0230","authenticated-orcid":false,"given":"Dae-Hyun","family":"Kim","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4846-4133","authenticated-orcid":false,"given":"Kihan","family":"Kim","sequence":"additional","affiliation":[]},{"given":"Sang-Yun","family":"Kim","sequence":"additional","affiliation":[]},{"given":"Dukha","family":"Park","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5773-0296","authenticated-orcid":false,"given":"Youngil","family":"Lim","sequence":"additional","affiliation":[]},{"given":"Geuntae","family":"Park","sequence":"additional","affiliation":[]},{"given":"Seung-Jun","family":"Lee","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5064-4152","authenticated-orcid":false,"given":"Seungki","family":"Hong","sequence":"additional","affiliation":[]},{"given":"Dae-Hyun","family":"Kwon","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2770-0560","authenticated-orcid":false,"given":"Isak","family":"Hwang","sequence":"additional","affiliation":[]},{"given":"Byongwook","family":"Na","sequence":"additional","affiliation":[]},{"given":"Kyung-Ryun","family":"Kim","sequence":"additional","affiliation":[]},{"given":"Seouk-Kyu","family":"Choi","sequence":"additional","affiliation":[]},{"given":"Hyein","family":"Choi","sequence":"additional","affiliation":[]},{"family":"Hangi-Jung","sequence":"additional","affiliation":[]},{"given":"Won-Il","family":"Bae","sequence":"additional","affiliation":[]},{"given":"Jeong-Don","family":"Ihm","sequence":"additional","affiliation":[]},{"given":"Seung-Jun","family":"Bae","sequence":"additional","affiliation":[]},{"given":"Nam Sung","family":"Kim","sequence":"additional","affiliation":[]},{"given":"Jung-Bae","family":"Lee","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2204475"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.903076"},{"key":"ref12","first-page":"314","article-title":"A 20nm 9Gb\/s\/pin 8Gb GDDR5 DRAM with an NBTI monitor, jitter reduction techniques and improved power distribution","author":"joo","year":"2016","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref13","first-page":"446","article-title":"A 16Gb\/s source-series terminated transmitter in 65nm CMOS SOI","author":"menolfi","year":"2007","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref14","first-page":"138","article-title":"Wide-range fast-lock duty-cycle corrector with offset-tolerant duty-cycle detection scheme for 54nm 7Gb\/s GDDR5 DRAM interface","author":"shin","year":"2009","journal-title":"Symp VLSI Circuits Dig Tech Papers"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2015.7231255"},{"key":"ref16","first-page":"204","article-title":"A 16Gb 18Gb\/S\/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking","author":"kim","year":"2018","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref17","first-page":"278","article-title":"A 60nm 6Gb\/s\/pin GDDR5 graphics DRAM with multifaceted clocking and ISI\/SSN-reduction techniques","author":"bae","year":"2008","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref18","first-page":"314","article-title":"A double-tail latch-type voltage sense amplifier with 18ps setup+hold time","author":"schinkel","year":"2007","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2850937"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2085991"},{"key":"ref3","first-page":"206","article-title":"A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm class DRAM process","author":"chun","year":"2018","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.908002"},{"key":"ref5","first-page":"40","article-title":"A 1.2V 38nm 2.4Gb\/s\/pin 2Gb DDR4 SDRAM with bank group and $\\times4$\n half-page architecture","author":"koo","year":"2012","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.1996.507748"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/92.365453"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2017.7870425"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2938396"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.914336"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/9306027\/09184953.pdf?arnumber=9184953","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,10]],"date-time":"2022-05-10T14:55:00Z","timestamp":1652194500000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9184953\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,1]]},"references-count":19,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2020.3017775","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2021,1]]}}}