{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,26]],"date-time":"2026-07-26T10:03:30Z","timestamp":1785060210835,"version":"3.55.0"},"reference-count":45,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"12","license":[{"start":{"date-parts":[[2020,12,1]],"date-time":"2020-12-01T00:00:00Z","timestamp":1606780800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,12,1]],"date-time":"2020-12-01T00:00:00Z","timestamp":1606780800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,12,1]],"date-time":"2020-12-01T00:00:00Z","timestamp":1606780800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"name":"Infineon Technologies AG"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2020,12]]},"DOI":"10.1109\/jssc.2020.3019344","type":"journal-article","created":{"date-parts":[[2020,9,3]],"date-time":"2020-09-03T22:41:00Z","timestamp":1599172860000},"page":"3349-3361","source":"Crossref","is-referenced-by-count":97,"title":["A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-<i>N<\/i> Bang\u2013Bang PLL With Digital Frequency-Error Recovery for Fast Locking"],"prefix":"10.1109","volume":"55","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-2301-5702","authenticated-orcid":false,"given":"Alessio","family":"Santiccioli","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0847-9207","authenticated-orcid":false,"given":"Mario","family":"Mercandelli","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6167-6512","authenticated-orcid":false,"given":"Luca","family":"Bertulessi","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-1397-9011","authenticated-orcid":false,"given":"Angelo","family":"Parisi","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Dmytro","family":"Cherniak","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0315-514X","authenticated-orcid":false,"given":"Andrea L.","family":"Lacaita","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7084-0721","authenticated-orcid":false,"given":"Carlo","family":"Samori","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0895-1700","authenticated-orcid":false,"given":"Salvatore","family":"Levantino","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1049\/el.2016.4577"},{"key":"ref38","doi-asserted-by":"crossref","first-page":"428","DOI":"10.1109\/JSSC.2015.2497963","article-title":"A 4-to-10.5 Gb\/s continuous-rate digital clock and data recovery with automatic frequency acquisition","volume":"51","author":"shu","year":"2016","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref33","first-page":"280","article-title":"A 170 MHz-lock-in-range and ?253dB-FoMjitter 12-to-14.5GHz subsampling PLL with a $150\\mu\\text{W}$\n frequency-disturbance-correcting loop using a low-power unevenly spaced edge generator","author":"lim","year":"2020","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref32","first-page":"266","article-title":"A ?240dB-FoM$_{jitter}$\n and ?115dBc\/Hz PN 100 kHz, 7.7 GHz ring-DCO-based digital PLL using P\/I-gain co-optimization and sequence-rearranged optimally spaced TDC for flicker-noise reduction","author":"lee","year":"2020","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2682841"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2742518"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2314436"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2157259"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.910966"},{"key":"ref34","article-title":"Theory and implementation of digital bang-bang frequency synthesizers for high speed serial data communications","author":"da dalt","year":"2007"},{"key":"ref10","first-page":"1665","article-title":"A 0.65-V 12-16-GHz sub-sampling PLL with 56.4-fs$_{rms}$\n integrated jitter and ?256.4-dB FoM","volume":"55","author":"zhang","year":"2020","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/4.848214"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2596766"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2539344"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2403373"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2016.7417963"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2959513"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2162917"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2272340"},{"key":"ref18","first-page":"268","article-title":"15.2 A 0.012 mm2 3.1mW bang-bang digital fractional-N PLL with a power-supply-noise cancellation technique and a walking-one-phase-selection fractional frequency divider","author":"liu","year":"2014","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2018.8310279"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2018.8310276"},{"key":"ref4","article-title":"A 164fs$_{rms}$\n 9-to-18GHz sampling phase detector based PLL with in-band noise suppression and robust frequency acquisition in 16nm FinFET","author":"raj","year":"2017","journal-title":"Proc Symp VLSI Circuits"},{"key":"ref27","first-page":"258","article-title":"A 76fs$_{rms}$\n jitter and ?40dBc integrated-phase-noise 28-to-31 GHz frequency synthesizer based on digital sub-sampling PLL using optimally spaced voltage comparators and background loop-gain optimization","author":"kim","year":"2019","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2018.8310342"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2018.8310282"},{"key":"ref29","first-page":"256","article-title":"A $265\\mu\\text{W}$\n fractional-N digital PLL with seamless automatic switching subsampling\/sampling feedback path and duty-cycled frequency-locked loop in 65nm CMOS","author":"liu","year":"2019","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref5","first-page":"256","article-title":"A 0.01 mm24.6-to-5.6GHz sub-sampling type-I frequency synthesizer with ?254dB FOM","author":"sharkia","year":"2018","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2889690"},{"key":"ref7","first-page":"270","article-title":"16.8 a 25.4-to-29.5GHz 10.2 mW isolated sub-sampling PLL achieving ?252.9dB jitter-power FoM and ?63dBc reference spur","author":"yang","year":"2019","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2899726"},{"key":"ref9","first-page":"1542","article-title":"A sub-mW 2.4-GHz active-mixer-adopted sub-sampling PLL achieving an FoM of ?256 dB","volume":"55","author":"lee","year":"2020","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2820149"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/RFIC.2018.8428846"},{"key":"ref45","doi-asserted-by":"crossref","first-page":"117","DOI":"10.1109\/TCSII.2008.2010189","article-title":"Jitter analysis and a benchmarking Figure-of-Merit for phase-locked loops","volume":"56","author":"gao","year":"2009","journal-title":"IEEE Trans Circuits Syst II Exp Briefs"},{"key":"ref22","first-page":"268","article-title":"A 66fs$_{rms}$\nJitter 12.8-to-15.2 GHz fractional-N bang-bang PLL with digital frequency-error recovery for fast locking","author":"santiccioli","year":"2020","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2941259"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/RFIC.2015.7337704"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2546304"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2006.886896"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2946134"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2017.8094572"},{"key":"ref26","first-page":"172","article-title":"9.8 An $860\\mu\\text{W}$\n 2.1-to-2.7 GHz all-digital PLL-based frequency modulator with a DTC-assisted snapshot TDC for WPAN (Bluetooth Smart and ZigBee) applications","author":"chillara","year":"2014","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1017\/CBO9780511541131"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2385753"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/9268488\/09186276.pdf?arnumber=9186276","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,4,27]],"date-time":"2022-04-27T13:39:30Z","timestamp":1651066770000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9186276\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,12]]},"references-count":45,"journal-issue":{"issue":"12"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2020.3019344","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2020,12]]}}}