{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,31]],"date-time":"2026-01-31T05:37:53Z","timestamp":1769837873033,"version":"3.49.0"},"reference-count":21,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2021,1,1]],"date-time":"2021-01-01T00:00:00Z","timestamp":1609459200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,1,1]],"date-time":"2021-01-01T00:00:00Z","timestamp":1609459200000},"content-version":"am","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,1,1]],"date-time":"2021-01-01T00:00:00Z","timestamp":1609459200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,1,1]],"date-time":"2021-01-01T00:00:00Z","timestamp":1609459200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["CCF-1618065"],"award-info":[{"award-number":["CCF-1618065"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2021,1]]},"DOI":"10.1109\/jssc.2020.3027953","type":"journal-article","created":{"date-parts":[[2020,10,13]],"date-time":"2020-10-13T19:44:37Z","timestamp":1602618277000},"page":"55-65","source":"Crossref","is-referenced-by-count":17,"title":["A Dynamic Timing Enhanced DNN Accelerator With Compute-Adaptive Elastic Clock Chain Technique"],"prefix":"10.1109","volume":"56","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-4570-4613","authenticated-orcid":false,"given":"Tianyu","family":"Jia","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yuhao","family":"Ju","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2912-7294","authenticated-orcid":false,"given":"Jie","family":"Gu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2019.00012"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2841824"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2913098"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/3307650.3322268"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2016.7598292"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2912510"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2019.8662389"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080246"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC19947.2020.9063062"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2020229"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2018.8310261"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2018.8310262"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2017.7870452"},{"key":"ref5","doi-asserted-by":"crossref","first-page":"8","DOI":"10.1109\/JSSC.2015.2473655","article-title":"A 16 nm all-digital auto-calibrating adaptive clock distribution for supply voltage droop tolerance across a wide operating range","volume":"51","author":"bowman","year":"2016","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2601319"},{"key":"ref7","doi-asserted-by":"crossref","first-page":"18","DOI":"10.1109\/JSSC.2015.2457920","article-title":"Enabling wide autonomous DVFS in a 22 nm graphics execution core using a digitally controlled fully integrated voltage regulator","volume":"51","author":"kim","year":"2016","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2017.7870353"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.23919\/VLSIC.2019.8778056"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2616357"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080254"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2018.8502404"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"https:\/\/ieeexplore.ieee.org\/ielam\/4\/9306027\/9222216-aam.pdf","content-type":"application\/pdf","content-version":"am","intended-application":"syndication"},{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/9306027\/09222216.pdf?arnumber=9222216","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,10]],"date-time":"2022-05-10T14:55:00Z","timestamp":1652194500000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9222216\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,1]]},"references-count":21,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2020.3027953","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2021,1]]}}}