{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,28]],"date-time":"2026-03-28T17:56:23Z","timestamp":1774720583943,"version":"3.50.1"},"reference-count":32,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"6","license":[{"start":{"date-parts":[[2021,6,1]],"date-time":"2021-06-01T00:00:00Z","timestamp":1622505600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,6,1]],"date-time":"2021-06-01T00:00:00Z","timestamp":1622505600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,6,1]],"date-time":"2021-06-01T00:00:00Z","timestamp":1622505600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"name":"Research and Development Program in Key Areas of Guangdong Province","award":["2019B010116002"],"award-info":[{"award-number":["2019B010116002"]}]},{"DOI":"10.13039\/501100007156","name":"Hong Kong Innovation and Technology Fund","doi-asserted-by":"crossref","award":["GHP\/004\/18SZ"],"award-info":[{"award-number":["GHP\/004\/18SZ"]}],"id":[{"id":"10.13039\/501100007156","id-type":"DOI","asserted-by":"crossref"}]},{"name":"Research Grant Council General Research Fund","award":["16200419"],"award-info":[{"award-number":["16200419"]}]},{"DOI":"10.13039\/501100002367","name":"Pioneer Hundred Talents Program, Chinese Academy of Sciences","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100002367","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2021,6]]},"DOI":"10.1109\/jssc.2020.3028376","type":"journal-article","created":{"date-parts":[[2020,10,16]],"date-time":"2020-10-16T19:56:41Z","timestamp":1602878201000},"page":"1871-1885","source":"Crossref","is-referenced-by-count":18,"title":["A 0.25\u20130.4-V, Sub-0.11-mW\/GHz, 0.15\u20131.6-GHz PLL Using an Offset Dual-Path Architecture With Dynamic Charge Pumps"],"prefix":"10.1109","volume":"56","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-9009-9045","authenticated-orcid":false,"given":"Zhao","family":"Zhang","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9970-4988","authenticated-orcid":false,"given":"Guang","family":"Zhu","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0211-2394","authenticated-orcid":false,"given":"C. Patrick","family":"Yue","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2239114"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1049\/el.2010.2555"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.831598"},{"key":"ref10","first-page":"33","article-title":"A 0.5V 10MHz-to-100MHz $0.47~\\mu\\mathrm{z}$\n power scalable AD-PLL in 40nm CMOS","author":"hiraku","year":"2012","journal-title":"Proc Asian Solid State Circuits Conf (ASCC)"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2015.2407370"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2871632"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2843337"},{"key":"ref14","first-page":"330","article-title":"A 0.17-to-3.5 mW 0.15-to-5GHz SoC PLL with 15dB built-in supply noise rejection and self-bandwidth control in 14nm CMOS","author":"shen","year":"2016","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2014.6946100"},{"key":"ref16","doi-asserted-by":"crossref","first-page":"319","DOI":"10.1109\/TCSII.2014.2312800","article-title":"A 0.4-V, $90~\\sim~350$\n-MHz PLL with an active loop-filter charge pump","volume":"61","author":"moon","year":"2014","journal-title":"IEEE Trans Circuits Syst II Exp Briefs"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2196315"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2010.2089559"},{"key":"ref19","doi-asserted-by":"crossref","first-page":"339","DOI":"10.1109\/TCSII.2009.2019160","article-title":"Designing an ultralow-voltage phase-locked loop using a bulk-driven technique","volume":"56","author":"lo","year":"2009","journal-title":"IEEE Trans Circuits Syst II Exp Briefs"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2005716"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2020.2989415"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2511157"},{"key":"ref3","first-page":"414","article-title":"A 0.18 V 382 $\\mu\\mathrm{W}$\n Bluetooth low-energy (BLE) receiver with 1.33nW sleep power for energy-harvesting applications in 28 nm CMOS","author":"yu","year":"2017","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2876464"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2012.2215792"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2935556"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2012.2231021"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2280409"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2017.2705053"},{"key":"ref9","first-page":"190","article-title":"A 0.55V 100MHz ADPLL with $\\Delta\\Sigma$\n LDO and relaxation DCO in 65nm CMOS","author":"zhang","year":"2015","journal-title":"Proc IEEE Int Symp Radio-Freq Integr Technol (RFIT)"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2707392"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/RFIC.2013.6569625"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/LMWC.2017.2662001"},{"key":"ref21","first-page":"164","article-title":"A 0.5-V 1.9-GHz low-power phase-locked loop in 0.18-$\\mu\\mathrm{m}$\n CMOS","author":"hsieh","year":"2007","journal-title":"Proc IEEE Symp VLSI Circuits"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2018.2797280"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2019.2910075"},{"key":"ref26","first-page":"1665","article-title":"A 0.65-V 12–16-GHz sub-sampling PLL with 56.4-fs$_{rms}$\n integrated jitter and–256.4-dB FoM","volume":"55","author":"zhang","year":"2020","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref25","first-page":"158c","article-title":"A 0.25-0.4 V, sub-0.11 mW\/GHz, 0.15-1.6GHz PLL using an offset dual-path loop architecture with dynamic charge pumps","author":"zhang","year":"2019","journal-title":"Proc Symp VLSI Circuits"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/9440831\/09226441.pdf?arnumber=9226441","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,10]],"date-time":"2022-05-10T14:54:52Z","timestamp":1652194492000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9226441\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,6]]},"references-count":32,"journal-issue":{"issue":"6"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2020.3028376","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2021,6]]}}}