{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,6]],"date-time":"2026-01-06T13:38:08Z","timestamp":1767706688159,"version":"3.37.3"},"reference-count":10,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2021,1,1]],"date-time":"2021-01-01T00:00:00Z","timestamp":1609459200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,1,1]],"date-time":"2021-01-01T00:00:00Z","timestamp":1609459200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,1,1]],"date-time":"2021-01-01T00:00:00Z","timestamp":1609459200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2021,1]]},"DOI":"10.1109\/jssc.2020.3028393","type":"journal-article","created":{"date-parts":[[2020,10,21]],"date-time":"2020-10-21T19:56:06Z","timestamp":1603310166000},"page":"225-234","source":"Crossref","is-referenced-by-count":9,"title":["A 128Gb 1-bit\/Cell 96-Word-Line-Layer 3D Flash Memory to Improve the Random Read Latency With tProg = 75 <i>\u03bc<\/i>s and tR = 4 <i>\u03bc<\/i>s"],"prefix":"10.1109","volume":"56","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-4616-1366","authenticated-orcid":false,"given":"Toshiyuki","family":"Kouchi","sequence":"first","affiliation":[]},{"given":"Mami","family":"Kakoi","sequence":"additional","affiliation":[]},{"given":"Noriyasu","family":"Kumazaki","sequence":"additional","affiliation":[]},{"given":"Akio","family":"Sugahara","sequence":"additional","affiliation":[]},{"given":"Akihiro","family":"Imamoto","sequence":"additional","affiliation":[]},{"given":"Yasufumi","family":"Kajiyama","sequence":"additional","affiliation":[]},{"given":"Yuri","family":"Terada","sequence":"additional","affiliation":[]},{"given":"Bushnaq","family":"Sanad","sequence":"additional","affiliation":[]},{"given":"Naoaki","family":"Kanagawa","sequence":"additional","affiliation":[]},{"given":"Takuyo","family":"Kodama","sequence":"additional","affiliation":[]},{"given":"Ryo","family":"Fukuda","sequence":"additional","affiliation":[]},{"given":"Hiromitsu","family":"Komai","sequence":"additional","affiliation":[]},{"given":"Norichika","family":"Asaoka","sequence":"additional","affiliation":[]},{"given":"Hidekazu","family":"Ohnishi","sequence":"additional","affiliation":[]},{"given":"Ryosuke","family":"Isomura","sequence":"additional","affiliation":[]},{"given":"Takaya","family":"Handa","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2037-4419","authenticated-orcid":false,"given":"Kensuke","family":"Yamamoto","sequence":"additional","affiliation":[]},{"given":"Yuki","family":"Ishizaki","sequence":"additional","affiliation":[]},{"given":"Yoko","family":"Deguchi","sequence":"additional","affiliation":[]},{"given":"Atsushi","family":"Okuyama","sequence":"additional","affiliation":[]},{"given":"Junichi","family":"Sato","sequence":"additional","affiliation":[]},{"given":"Hiroki","family":"Yabe","sequence":"additional","affiliation":[]},{"given":"Hua-Ling Cynthia","family":"Hsu","sequence":"additional","affiliation":[]},{"given":"Masahiro","family":"Yoshihara","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","first-page":"422","article-title":"A 19nm 112.8 mm2 64Gb multi-level flash memory with 400Mb\/s\/pin 1.8 V toggle mode interface","author":"shibata","year":"2012","journal-title":"Proc IEEE Int Solid-State Circuits Conf"},{"key":"ref3","first-page":"338","article-title":"A flash memory controller for 15?s ultra-low-latency SSD using high-speed 3D NAND flash with 3?s read time","author":"cheong","year":"2018","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2015.7062964"},{"year":"2019","key":"ref6"},{"key":"ref5","first-page":"218","article-title":"13.5 A 512Gb 3-bit\/cell 3D flash memory on 128-wordline-layer with 132MB\/s write performance featuring circuit-under-array technology","author":"siau","year":"2019","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2018.8310323"},{"key":"ref7","first-page":"130","article-title":"7.1 256Gb 3b\/cell V-NAND flash memory with 48 stacked WL layers","author":"kang","year":"2016","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2019.2905852"},{"key":"ref9","first-page":"210","article-title":"A 1.33Tb 4-bit\/cell 3D-flash memory on a 96-word-line-layer technology","author":"shibata","year":"2012","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2018.8310321"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/9306027\/09234438.pdf?arnumber=9234438","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,10]],"date-time":"2022-05-10T14:55:00Z","timestamp":1652194500000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9234438\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,1]]},"references-count":10,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2020.3028393","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"type":"print","value":"0018-9200"},{"type":"electronic","value":"1558-173X"}],"subject":[],"published":{"date-parts":[[2021,1]]}}}