{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,30]],"date-time":"2025-10-30T07:13:31Z","timestamp":1761808411562,"version":"3.37.3"},"reference-count":45,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"6","license":[{"start":{"date-parts":[[2021,6,1]],"date-time":"2021-06-01T00:00:00Z","timestamp":1622505600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,6,1]],"date-time":"2021-06-01T00:00:00Z","timestamp":1622505600000},"content-version":"am","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,6,1]],"date-time":"2021-06-01T00:00:00Z","timestamp":1622505600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,6,1]],"date-time":"2021-06-01T00:00:00Z","timestamp":1622505600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100012166","name":"National Key Research and Development Program of China","doi-asserted-by":"publisher","award":["2019YFB2204204"],"award-info":[{"award-number":["2019YFB2204204"]}],"id":[{"id":"10.13039\/501100012166","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"NSFC","doi-asserted-by":"publisher","award":["61674094","61934005","61720106013"],"award-info":[{"award-number":["61674094","61934005","61720106013"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100017582","name":"Beijing National Research Center for Information Science and Technology","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100017582","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100012282","name":"Beijing Innovation Center for Future Chips","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100012282","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["CNS-1739748"],"award-info":[{"award-number":["CNS-1739748"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2021,6]]},"DOI":"10.1109\/jssc.2020.3030264","type":"journal-article","created":{"date-parts":[[2020,11,2]],"date-time":"2020-11-02T21:23:46Z","timestamp":1604352226000},"page":"1936-1948","source":"Crossref","is-referenced-by-count":11,"title":["STICKER-T: An Energy-Efficient Neural Network Processor Using Block-Circulant Algorithm and Unified Frequency-Domain Acceleration"],"prefix":"10.1109","volume":"56","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-8234-7400","authenticated-orcid":false,"given":"Jinshan","family":"Yue","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4892-2309","authenticated-orcid":false,"given":"Yongpan","family":"Liu","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9873-6574","authenticated-orcid":false,"given":"Ruoyang","family":"Liu","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4793-0972","authenticated-orcid":false,"given":"Wenyu","family":"Sun","sequence":"additional","affiliation":[]},{"given":"Zhe","family":"Yuan","sequence":"additional","affiliation":[]},{"given":"Yung-Ning","family":"Tu","sequence":"additional","affiliation":[]},{"given":"Yi-Ju","family":"Chen","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2322-8038","authenticated-orcid":false,"given":"Ao","family":"Ren","sequence":"additional","affiliation":[]},{"given":"Yanzhi","family":"Wang","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6905-6350","authenticated-orcid":false,"given":"Meng-Fan","family":"Chang","sequence":"additional","affiliation":[]},{"given":"Xueqing","family":"Li","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2421-353X","authenticated-orcid":false,"given":"Huazhong","family":"Yang","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1984.1676458"},{"key":"ref38","first-page":"131","article-title":"Design and implementation of a 1024-point pipeline FFT processor","author":"he","year":"1998","journal-title":"Proc IEEE Custom Integr Circuits Conf"},{"journal-title":"DataDJI Image Detection Dataset","year":"2018","key":"ref33"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2009.5206848"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-030-01237-3_12"},{"key":"ref30","article-title":"DoReFa-net: Training low bitwidth convolutional neural networks with low bitwidth gradients","author":"zhou","year":"2016","journal-title":"arXiv 1606 06160 [cs]"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/SCOPES.2016.7955712"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.852007"},{"journal-title":"The MNIST dataset of handwritten digits","year":"2018","key":"ref35"},{"journal-title":"TIMIT Speech Recognition Dataset","year":"2018","key":"ref34"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2017.7870353"},{"key":"ref40","first-page":"138","article-title":"7.5 a 65 nm 0.39-to-140.3TOPS\/W 1-to-12b unified neural network processor using block-circulant-enabled transpose-domain acceleration with 8.1 &#x00D7; higher TOPS\/mm&#x00B2; and 6T HBST-TRAM-Based 2D data-reuse architecture","author":"yue","year":"2019","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2616357"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2016.7573525"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/A-SSCC47793.2019.9056918"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2636225"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2017.7870350"},{"key":"ref16","first-page":"250","article-title":"14.7 a 288 ?W programmable deep-learning processor with 270KB on-chip weight storage using non-uniform memory hierarchy for mobile intelligence","author":"bang","year":"2017","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref17","article-title":"Deep compression: Compressing deep neural networks with pruning, trained quantization and Huffman coding","author":"han","year":"2015","journal-title":"arXiv 1510 00149 [cs]"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-030-01237-3_12"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2016.7783723"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/3123939.3124552"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2016.90"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080246"},{"key":"ref3","article-title":"Very deep convolutional networks for large-scale image recognition","author":"simonyan","year":"2014","journal-title":"arXiv 1409 1556"},{"key":"ref6","article-title":"MobileNets: Efficient convolutional neural networks for mobile vision applications","author":"howard","year":"2017","journal-title":"arXiv 1704 04861"},{"key":"ref29","article-title":"Long short-term memory recurrent neural network architectures for large scale acoustic modeling","author":"sak","year":"2014","journal-title":"arXiv 1402 1128"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2017.243"},{"key":"ref8","article-title":"An analysis of deep neural network models for practical applications","author":"canziani","year":"2016","journal-title":"arXiv 1605 07678"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2016.91"},{"key":"ref2","first-page":"1097","article-title":"Imagenet classification with deep convolutional neural networks","author":"krizhevsky","year":"2012","journal-title":"Proc Adv Neural Inf Process Syst"},{"key":"ref9","first-page":"242","article-title":"14.3 a 28 nm SoC with a 1.2GHz 568nJ\/prediction sparse deep-neural-network engine with >0.1 timing error rate tolerance for IoT applications","author":"whatmough","year":"2017","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref1","doi-asserted-by":"crossref","first-page":"436","DOI":"10.1038\/nature14539","article-title":"Deep learning","volume":"521","author":"lecun","year":"2015","journal-title":"Nature"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001163"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.23919\/VLSIC.2019.8778056"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2018.8502404"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001138"},{"key":"ref42","first-page":"1","article-title":"A 45 nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons","author":"seo","year":"2011","journal-title":"Proc IEEE Custom Integr Circuits Conf (CICC)"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/2847263.2847265"},{"key":"ref41","first-page":"248","article-title":"14.6 a 0.62 mW ultra-low-power convolutional-neural-network face-recognition processor and a CIS integrated with always-on Haar-like face detector","author":"bong","year":"2017","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080254"},{"key":"ref44","first-page":"134","article-title":"7.1 a 3.4-to-13.3TOPS\/W 3.6TOPS dual-core deep-learning accelerator for versatile AI applications in 7 nm 5G smartphone SoC","author":"lin","year":"2020","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2778281"},{"key":"ref43","first-page":"232","article-title":"14.2 a 65nm 24.7 ?J\/Frame 12.3 mW Activation-Similarity-Aware convolutional neural network video processor using hybrid precision, inter-frame data reuse and Mixed-Bit-Width difference-frame data codec","author":"yuan","year":"2020","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2018.8310262"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"https:\/\/ieeexplore.ieee.org\/ielam\/4\/9440831\/9246543-aam.pdf","content-type":"application\/pdf","content-version":"am","intended-application":"syndication"},{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/9440831\/09246543.pdf?arnumber=9246543","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,10]],"date-time":"2022-05-10T14:54:52Z","timestamp":1652194492000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9246543\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,6]]},"references-count":45,"journal-issue":{"issue":"6"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2020.3030264","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"type":"print","value":"0018-9200"},{"type":"electronic","value":"1558-173X"}],"subject":[],"published":{"date-parts":[[2021,6]]}}}