{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,11]],"date-time":"2026-03-11T16:48:55Z","timestamp":1773247735244,"version":"3.50.1"},"reference-count":56,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2021,1,1]],"date-time":"2021-01-01T00:00:00Z","timestamp":1609459200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"name":"French National Program Programme d\u2019Investissements d\u2019Avenir, IRT Nanoelec","award":["ANR-10-AIRT-05"],"award-info":[{"award-number":["ANR-10-AIRT-05"]}]},{"name":"SHARP CA109 CATRENE Project"},{"name":"MASTER3D CT312 CATRENE Project"},{"name":"Hubeo+ CARNOT Project"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2021,1]]},"DOI":"10.1109\/jssc.2020.3036341","type":"journal-article","created":{"date-parts":[[2020,12,10]],"date-time":"2020-12-10T16:25:08Z","timestamp":1607617508000},"page":"79-97","source":"Crossref","is-referenced-by-count":117,"title":["IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management"],"prefix":"10.1109","volume":"56","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-7413-8243","authenticated-orcid":false,"given":"Pascal","family":"Vivet","sequence":"first","affiliation":[]},{"given":"Eric","family":"Guthmuller","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7721-5796","authenticated-orcid":false,"given":"Yvain","family":"Thonnart","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0539-7185","authenticated-orcid":false,"given":"Gael","family":"Pillonnet","sequence":"additional","affiliation":[]},{"given":"Cesar","family":"Fuguet","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7719-661X","authenticated-orcid":false,"given":"Ivan","family":"Miro-Panades","sequence":"additional","affiliation":[]},{"given":"Guillaume","family":"Moritz","sequence":"additional","affiliation":[]},{"given":"Jean","family":"Durupt","sequence":"additional","affiliation":[]},{"given":"Christian","family":"Bernard","sequence":"additional","affiliation":[]},{"given":"Didier","family":"Varreau","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1249-1631","authenticated-orcid":false,"given":"Julian","family":"Pontes","sequence":"additional","affiliation":[]},{"given":"Sebastien","family":"Thuries","sequence":"additional","affiliation":[]},{"given":"David","family":"Coriat","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4423-4805","authenticated-orcid":false,"given":"Michel","family":"Harrand","sequence":"additional","affiliation":[]},{"given":"Denis","family":"Dutoit","sequence":"additional","affiliation":[]},{"given":"Didier","family":"Lattard","sequence":"additional","affiliation":[]},{"given":"Lucile","family":"Arnaud","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0003-3769-3712","authenticated-orcid":false,"given":"Jean","family":"Charbonnier","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0003-1727-4529","authenticated-orcid":false,"given":"Perceval","family":"Coudrain","sequence":"additional","affiliation":[]},{"given":"Arnaud","family":"Garnier","sequence":"additional","affiliation":[]},{"given":"Frederic","family":"Berger","sequence":"additional","affiliation":[]},{"given":"Alain","family":"Gueugnot","sequence":"additional","affiliation":[]},{"given":"Alain","family":"Greiner","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8848-8079","authenticated-orcid":false,"given":"Quentin L.","family":"Meunier","sequence":"additional","affiliation":[]},{"given":"Alexis","family":"Farcy","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7926-3513","authenticated-orcid":false,"given":"Alexandre","family":"Arriordaz","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1473-5572","authenticated-orcid":false,"given":"Severine","family":"Cheramy","sequence":"additional","affiliation":[]},{"given":"Fabien","family":"Clermidy","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/MDAT.2015.2413759"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2015.7058997"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/ECCE.2011.6064205"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2017.2767585"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2018.8310172"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/IOLTS.2017.8046240"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2019.00014"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2611497"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/TPEL.2015.2478850"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/TPEL.2016.2530745"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2012.36"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/2830772.2830832"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI-SoC.2013.6673297"},{"key":"ref2","volume":"1","author":"ramm","year":"2008","journal-title":"Handbook of 3D Integration Technology and Applications of 3D"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2019.00068"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/3313231.3352380"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/S3S.2017.8309222"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC19947.2020.9062927"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2018.8494275"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC.2019.00092"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/NEWCAS.2017.8010109"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/ASAP.2018.8445107"},{"key":"ref50","year":"2011","journal-title":"Calibre 3D STACK"},{"key":"ref51","year":"2014"},{"key":"ref56","article-title":"Thermal exploration and sign-off analysis for advanced 3D integration","author":"santos","year":"2017","journal-title":"Proc Design Track DAC Conf"},{"key":"ref55","article-title":"A complete guide to 3D chip-package thermal co-design, 10 key considerations","author":"graphics","year":"2017"},{"key":"ref54","doi-asserted-by":"publisher","DOI":"10.1109\/3DIC.2014.7152163"},{"key":"ref53","doi-asserted-by":"publisher","DOI":"10.1109\/3DIC.2014.7152182"},{"key":"ref52","first-page":"55","article-title":"Thermal analysis of hot spots in advanced 3D-stacked structures","author":"torregiani","year":"2009","journal-title":"Proc Int Workshop Therm Invest ICs Syst"},{"key":"ref10","first-page":"1","article-title":"Quality in 3D assembly—Is, known good die good enough?","author":"quinne","year":"0","journal-title":"Proc IEEE Int 3D Syst Integr Conf (3DIC)"},{"key":"ref11","first-page":"316","article-title":"18.2 a 1.2 V 20nm 307GB\/s HBM DRAM with at-speed wafer-level I\/O test scheme and adaptive refresh considering temperature distribution","author":"sohn","year":"2016","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2020.2970724"},{"key":"ref12","article-title":"14.3 a 43pJ\/Cycle non-volatile microcontroller with 4.7s Shutdown\/Wake-up integrating 2.3-bit\/Cell resistive RAM and resilience techniques","author":"wu","year":"2019","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/3DIC48104.2019.9058905"},{"key":"ref14","year":"2019","journal-title":"Open Computer Project"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC19947.2020.9063103"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC19947.2020.9062957"},{"key":"ref17","first-page":"222","article-title":"Active-lite interposer for 2.5 & 3D integration","author":"hellings","year":"2015","journal-title":"Proc Symp VLSI Technol Circuits"},{"key":"ref18","first-page":"35","article-title":"The active-interposer concept for high-performance chip-to-chip connections","volume":"5","author":"ch\u00e9ramy","year":"2014","journal-title":"Chip Scale Rev"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2018.00066"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2018.8310173"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC.2019.00095"},{"key":"ref6","first-page":"54","article-title":"A 14nm 1GHz FPGA with 2.5D transceiver integration","author":"greenhill","year":"2017","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.23919\/VLSIC.2019.8778161"},{"key":"ref8","year":"2017","journal-title":"CHIPS Program"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/MSPEC.2019.8847587"},{"key":"ref49","first-page":"1","article-title":"Multi-Die IC Design Tutorial","author":"reiter","year":"2015","journal-title":"Proc 3D ASIP Conf"},{"key":"ref9","year":"2020","journal-title":"3 Ways Chiplets are Remaking Processors"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2369503"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/ETS.2016.7519310"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1109\/ACSSC.2014.7094761"},{"key":"ref47","article-title":"ExaNoDe: Combined integration of chiplets on active interposer with bare dice in a multi-chip-module for heterogeneous and scalable high performance compute nodes","author":"martinez","year":"2020","journal-title":"Proc IEEE VLSI Conf"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/MDAT.2015.2424422"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/ETS.2013.6569349"},{"key":"ref44","year":"2020","journal-title":"IEEE 1838 WG"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2013.6651893"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/9306027\/09290098.pdf?arnumber=9290098","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T11:46:58Z","timestamp":1641988018000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9290098\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,1]]},"references-count":56,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2020.3036341","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2021,1]]}}}