{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,11]],"date-time":"2026-03-11T17:08:45Z","timestamp":1773248925608,"version":"3.50.1"},"reference-count":37,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2021,4,1]],"date-time":"2021-04-01T00:00:00Z","timestamp":1617235200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,4,1]],"date-time":"2021-04-01T00:00:00Z","timestamp":1617235200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,4,1]],"date-time":"2021-04-01T00:00:00Z","timestamp":1617235200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2021,4]]},"DOI":"10.1109\/jssc.2020.3043786","type":"journal-article","created":{"date-parts":[[2020,12,30]],"date-time":"2020-12-30T21:30:41Z","timestamp":1609363841000},"page":"1166-1175","source":"Crossref","is-referenced-by-count":10,"title":["A Proactive System for Voltage-Droop Mitigation in a 7-nm Hexagon\u2122 Processor"],"prefix":"10.1109","volume":"56","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-4310-2846","authenticated-orcid":false,"given":"Vijay Kiran","family":"Kalyanam","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Eric","family":"Mahurin","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7638-9783","authenticated-orcid":false,"given":"Keith A.","family":"Bowman","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5336-5631","authenticated-orcid":false,"given":"Jacob A.","family":"Abraham","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/TCT.1971.1083367"},{"key":"ref32","author":"oppenheim","year":"1999","journal-title":"Discrete-Time Signal Processing"},{"key":"ref31","author":"oppenheim","year":"1997","journal-title":"Signals and Systems"},{"key":"ref30","author":"proakis","year":"1996","journal-title":"Digital Signal Processing Principles Algorithms and Applications"},{"key":"ref37","article-title":"Functional test sequences for inducing voltage droops in a multi-threaded processor","author":"kalyanam","year":"2020","journal-title":"Proc IEEE Int Test Conf (ITC)"},{"key":"ref36","article-title":"Implementing IIR\/FIR filters with Motorola’s DSP56000\/SPS\/DSP56001 digital signal processors","author":"lane","year":"1993"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/T-AIEE.1928.5055024"},{"key":"ref34","first-page":"3.1","article-title":"Finite wordlength effects","author":"bomar","year":"1998","journal-title":"The Digital Signal Processing Handbook"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2089657"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2014023"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2237972"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2014.6757359"},{"key":"ref14","doi-asserted-by":"crossref","first-page":"8","DOI":"10.1109\/JSSC.2015.2473655","article-title":"A 16 nm all-digital auto-calibrating adaptive clock distribution for supply voltage droop tolerance across a wide operating range","volume":"51","author":"bowman","year":"2016","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2218067"},{"key":"ref16","first-page":"321","article-title":"UVFR: A unified voltage and frequency regulator with 500 MHz\/0.84 V to 100 KHz\/0.27 V operating range, 99.4% current efficiency and 27% supply guardband reduction","author":"gangopadhyay","year":"2016","journal-title":"Proc 42nd Eur Solid-State Circuits Conf"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2018.8310304"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2018.8502303"},{"key":"ref19","first-page":"316","article-title":"A 7 nm all-digital unified voltage and frequency regulator based on a high-bandwidth 2-phase buck converter with package inductors","author":"atallah","year":"2019","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref28","article-title":"A proactive voltage-droop-mitigation system in a 7 nm Hexagon™ processor","author":"kalyanam","year":"2020","journal-title":"Proc IEEE Symp VLSI Circuits"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155622"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1147\/JRD.2020.3008143"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2007.373409"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2017.7870452"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2017.7918320"},{"key":"ref5","first-page":"106","article-title":"Adaptive clocking system for improved power efficiency in a 28 nm ×86-64 microprocessor","author":"grenat","year":"2014","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2007145"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.870912"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.859879"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2007148"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/HOTCHIPS.2015.7477329"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/MSSC.2018.2844601"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/1283780.1283808"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2002.995694"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2010.25"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2009.4798233"},{"key":"ref26","first-page":"54","article-title":"IBM z15: A 12-core 5.2 GHz microprocessor","author":"berry","year":"2020","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2018.8310303"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/9387173\/09311181.pdf?arnumber=9311181","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,10]],"date-time":"2022-05-10T14:54:55Z","timestamp":1652194495000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9311181\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,4]]},"references-count":37,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2020.3043786","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2021,4]]}}}