{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,19]],"date-time":"2026-06-19T15:56:26Z","timestamp":1781884586793,"version":"3.54.5"},"reference-count":38,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2021,4,1]],"date-time":"2021-04-01T00:00:00Z","timestamp":1617235200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,4,1]],"date-time":"2021-04-01T00:00:00Z","timestamp":1617235200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,4,1]],"date-time":"2021-04-01T00:00:00Z","timestamp":1617235200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2021,4]]},"DOI":"10.1109\/jssc.2020.3047431","type":"journal-article","created":{"date-parts":[[2021,1,13]],"date-time":"2021-01-13T19:50:23Z","timestamp":1610567423000},"page":"1254-1264","source":"Crossref","is-referenced-by-count":25,"title":["A Power-Efficient Fractional-N DPLL With Phase Error Quantized in Fully Differential-Voltage Domain"],"prefix":"10.1109","volume":"56","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-0457-2386","authenticated-orcid":false,"given":"Lianbo","family":"Wu","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1399-5444","authenticated-orcid":false,"given":"Thomas","family":"Burger","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1586-6988","authenticated-orcid":false,"given":"Philipp","family":"Schonle","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Qiuting","family":"Huang","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2602214"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2015.2477580"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2019.2909429"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.876206"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/81.855452"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2042254"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.818300"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1002\/0470041951"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/T-ED.1984.21550"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.870894"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.908763"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2273836"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2596766"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/LSSC.2020.2967744"},{"key":"ref15","first-page":"54","article-title":"A 5.3 GHz digital-to-time-converter-based fractional-N all-digital PLL","author":"pavlovic","year":"2011","journal-title":"Proc IEEE Int Solid-State Circuits Conf"},{"key":"ref16","first-page":"172","article-title":"9.8 An $860\\mu\\text{W}$\n 2.1-to-2.7 GHz all-digital PLL-based frequency modulator with a DTC-assisted snapshot TDC for WPAN (Bluetooth Smart and ZigBee) applications","author":"chillara","year":"2014","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2016.2625462"},{"key":"ref18","first-page":"3317","article-title":"A 2.2-GHz 3.2-mW DTC-free sampling $\\Delta\\Sigma$\n fractional-N PLL with ?110 dBc\/Hz in-band phase noise and ?246dB FoM and ?83dBc reference spur","author":"tao","year":"2019","journal-title":"Proc Symp VLSI Circuits"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2539344"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2047435"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2109432"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2014709"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2899726"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2301760"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.917405"},{"key":"ref5","doi-asserted-by":"crossref","first-page":"117","DOI":"10.1109\/TCSII.2008.2010189","article-title":"Jitter analysis and a benchmarking figure-of-merit for phase-locked loops","volume":"56","author":"gao","year":"2009","journal-title":"IEEE Trans Circuits Syst II Exp Briefs"},{"key":"ref8","first-page":"174","article-title":"9.6 A 2.7-to-4.3 GHz, 0.16psrms-jitter, ?246.8 dB-FOM, digital fractional-N sampling PLL in 28 nm CMOS","author":"gao","year":"2016","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/VLSICircuits18222.2020.9162777"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2742518"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2878836"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2018.8494248"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.857417"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2018.2855972"},{"key":"ref21","first-page":"190","article-title":"10.5 A digital PLL with feedforward multi-tone spur cancelation loop achieving ?73dBc fractional spur and ?110dBc reference spur in 65 nm CMOS","author":"ho","year":"2016","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2546304"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2582854"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2015.7063029"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2018.2857999"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/9387173\/09321137.pdf?arnumber=9321137","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,10]],"date-time":"2022-05-10T14:54:55Z","timestamp":1652194495000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9321137\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,4]]},"references-count":38,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2020.3047431","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2021,4]]}}}