{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,27]],"date-time":"2026-03-27T02:45:13Z","timestamp":1774579513464,"version":"3.50.1"},"reference-count":39,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"7","license":[{"start":{"date-parts":[[2021,7,1]],"date-time":"2021-07-01T00:00:00Z","timestamp":1625097600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,7,1]],"date-time":"2021-07-01T00:00:00Z","timestamp":1625097600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,7,1]],"date-time":"2021-07-01T00:00:00Z","timestamp":1625097600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100001381","name":"Singapore National Research Foundation","doi-asserted-by":"publisher","award":["NRF2018NCR-NCR002-0001"],"award-info":[{"award-number":["NRF2018NCR-NCR002-0001"]}],"id":[{"id":"10.13039\/501100001381","id-type":"DOI","asserted-by":"publisher"}]},{"name":"TSMC for chip fabrication support"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2021,7]]},"DOI":"10.1109\/jssc.2021.3050959","type":"journal-article","created":{"date-parts":[[2021,3,2]],"date-time":"2021-03-02T21:07:23Z","timestamp":1614719243000},"page":"2182-2192","source":"Crossref","is-referenced-by-count":24,"title":["PUF Architecture with Run-Time Adaptation for Resilient and Energy-Efficient Key Generation via Sensor Fusion"],"prefix":"10.1109","volume":"56","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-4590-7875","authenticated-orcid":false,"given":"Sachin","family":"Taneja","sequence":"first","affiliation":[{"name":"ECE Department, National University of Singapore, Singapore"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4127-8258","authenticated-orcid":false,"given":"Massimo","family":"Alioto","sequence":"additional","affiliation":[{"name":"ECE Department, National University of Singapore, Singapore"}]}],"member":"263","reference":[{"key":"ref39","author":"chatterjee","year":"2012","journal-title":"Regression Analysis by Example"},{"key":"ref38","author":"mohri","year":"2012","journal-title":"Foundations of Machine Learning"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1989.572629"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2013.2291091"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2010.203"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4419-8080-9"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2015.7063027"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2749423"},{"key":"ref35","first-page":"392","article-title":"A voltage and temperature tracking SRAM assist supporting 740 mV dual-rail offset for low-power and high-performance applications in 7 nm EUV FinFET technology","author":"lee","year":"2019","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/MSSC.2015.2418155"},{"key":"ref10","first-page":"161","article-title":"A 373F$^{2}~2\\text{D}$\n power-gated EE SRAM physically unclonable function with dark-bit detection technique","author":"liu","year":"2018","journal-title":"Proc IEEE Asian Solid-State Circuits Conf (A-SSCC)"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2017.7870303"},{"key":"ref12","doi-asserted-by":"crossref","first-page":"763","DOI":"10.1109\/JSSC.2015.2506641","article-title":"Static physically unclonable functions for secure chip identification with 1.9–5.8% native bit instability at 0.6–1 V and 15 fJ\/bit in 65 nm","volume":"51","author":"alvarez","year":"2016","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2586498"},{"key":"ref14","first-page":"426","article-title":"Physically unclonable function in 28 nm FDSOI technology achieving high reliability for AEC-Q 100 grade 1 and ISO 26262 ASIL-B","author":"choi","year":"2020","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2791460"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2018.8310219"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2019.8662537"},{"key":"ref18","first-page":"278","article-title":"A 0.19pJ\/b PVT-variation-tolerant hybrid physically unclonable function circuit for 100% stable secure key generation in 22 nm CMOS","author":"mathew","year":"2014","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref19","first-page":"1","article-title":"An efficient reliable PUF-based cryptographic key generator in 65 nm CMOS","author":"bhargava","year":"2014","journal-title":"Proc Design Autom Test Eur Conf Exhibition (DATE)"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/FDTC.2013.19"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/MSSC.2017.2745799"},{"key":"ref27","author":"maes","year":"2010","journal-title":"Towards Hardware-Intrinsic Security"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/MSSC.2019.2923503"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2019.8780123"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/FDTC.2015.19"},{"key":"ref5","first-page":"9","article-title":"Physical unclonable functions for device authentication and secret key generation","author":"suh","year":"2007","journal-title":"Proc 44th ACM\/IEEE Design Autom Conf"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2636859"},{"key":"ref7","first-page":"158","article-title":"Physically unclonable function for secure key generation with a key error rate of 2E-38 in 45 nm smart-card chips","author":"karpinskyy","year":"2016","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-51482-6"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2865584"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-41395-7"},{"key":"ref20","article-title":"Apparatus and method for generating identification key","author":"choi","year":"2018"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2920714"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2018.8310218"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2019.8902733"},{"key":"ref23","first-page":"239","article-title":"13fJ\/bit probing-resilient 250K PUF array with soft darkbit masking for 1.94% bit-error in 22 nm tri-gate CMOS","author":"satpathy","year":"2014","journal-title":"Proc ESSCIRC-40th Eur Solid State Circuits Conf (ESSCIRC)"},{"key":"ref26","author":"alioto","year":"2020","journal-title":"HW Security Primitives Database"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/JIOT.2018.2875472"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/9466892\/09367184.pdf?arnumber=9367184","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,4,29]],"date-time":"2025-04-29T17:32:03Z","timestamp":1745947923000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9367184\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,7]]},"references-count":39,"journal-issue":{"issue":"7"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2021.3050959","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2021,7]]}}}