{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,24]],"date-time":"2026-03-24T00:46:28Z","timestamp":1774313188598,"version":"3.50.1"},"reference-count":43,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"7","license":[{"start":{"date-parts":[[2021,7,1]],"date-time":"2021-07-01T00:00:00Z","timestamp":1625097600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,7,1]],"date-time":"2021-07-01T00:00:00Z","timestamp":1625097600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,7,1]],"date-time":"2021-07-01T00:00:00Z","timestamp":1625097600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"name":"RIE2020 ASTAR AME IAF-ICP","award":["I1801E0030"],"award-info":[{"award-number":["I1801E0030"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2021,7]]},"DOI":"10.1109\/jssc.2021.3061508","type":"journal-article","created":{"date-parts":[[2021,3,9]],"date-time":"2021-03-09T21:40:05Z","timestamp":1615326005000},"page":"2221-2233","source":"Crossref","is-referenced-by-count":167,"title":["Colonnade: A Reconfigurable SRAM-Based Digital Bit-Serial Compute-In-Memory Macro for Processing Neural Networks"],"prefix":"10.1109","volume":"56","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-9906-073X","authenticated-orcid":false,"given":"Hyunjoon","family":"Kim","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9876-7725","authenticated-orcid":false,"given":"Taegeun","family":"Yoo","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1779-1799","authenticated-orcid":false,"given":"Tony Tae-Hyoung","family":"Kim","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5397-9628","authenticated-orcid":false,"given":"Bongjin","family":"Kim","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref39","first-page":"240","article-title":"15.2 A 28 nm 64Kb inference-training two-way transpose multibit 6T SRAM compute-in-memory macro for AI edge chips","author":"su","year":"2020","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/5.726791"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/CICC48029.2020.9075883"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/A-SSCC47793.2019.9056926"},{"key":"ref31","first-page":"246","article-title":"Envision: A 0.26-to-10 TOPS\/W subword-parallel dynamic-voltage-accuracy-frequency-scalable convolutional neural network processor in 28 nm FDSOI","author":"moons","year":"2017","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2017.7870350"},{"key":"ref37","first-page":"1097","article-title":"ImageNet classification with deep convolutional neural networks","author":"krizhevsky","year":"2012","journal-title":"Proc Adv Neural Inf Process Syst (NIPS)"},{"key":"ref36","article-title":"Very deep convolutional networks for large-scale image recognition","author":"simonyan","year":"2014","journal-title":"arXiv 1409 1556"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2019.8902824"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080246"},{"key":"ref10","article-title":"XNOR-Net: ImageNet classification using binary convolutional neural networks","author":"rastegari","year":"2016","journal-title":"arXiv 1603 05279"},{"key":"ref40","first-page":"246","article-title":"15.5 A 28 nm 64Kb 6T SRAM computing-in-memory macro with 8b MAC operation for AI edge chips","author":"si","year":"2020","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref11","article-title":"Binarized neural networks: Training deep neural networks with weights and activations constrained to +1 or ?1","author":"courbariaux","year":"2016","journal-title":"arXiv 1602 02830 [cs]"},{"key":"ref12","article-title":"BinaryConnect: Training deep neural networks with binary weights during propagations","author":"courbariaux","year":"2015","journal-title":"arXiv 1511 00363"},{"key":"ref13","first-page":"1","article-title":"Quantized neural networks: Training neural networks with low precision weights and activations","volume":"18","author":"hubara","year":"2018","journal-title":"J Mach Learn Res"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2939682"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2884901"},{"key":"ref16","first-page":"140","article-title":"7.6 A 65 nm 236.5 nJ\/classification neuromorphic processor with 7.5% energy overhead on-chip learning using direct spike-only feedback","author":"park","year":"2019","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.58"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001163"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2016.7783722"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2018.00040"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2899730"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2750389"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2880918"},{"key":"ref6","first-page":"490","article-title":"A 42 pJ\/decision 3.12 TOPS\/W robust in-memory machine learning classifier with on-chip training","author":"gonugondla","year":"2018","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001165"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2963616"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2865489"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2616357"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2782087"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2881913"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2778702"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2018.00069"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2636225"},{"key":"ref21","first-page":"10","article-title":"1.1 computing’s energy problem (and what we can do about it)","author":"horowitz","year":"2014","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2019.8662392"},{"key":"ref24","article-title":"Model compression via distillation and quantization","author":"polino","year":"2018","journal-title":"Proc Int Conf Learn Represent (ICLR)"},{"key":"ref41","first-page":"496","article-title":"A 65 nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3 ns and 55.8 TOPS\/W fully parallel product-sum operation for binary DNN edge processors","author":"khwa","year":"2018","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref23","article-title":"Quantizing deep convolutional networks for efficient inference: A whitepaper","author":"krishnamoorthi","year":"2018","journal-title":"arXiv 1806 08342"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2778281"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1145\/3307650.3322257"},{"key":"ref25","article-title":"Incremental network quantization: Towards lossless CNNs with low-precision weights","author":"zhou","year":"2017","journal-title":"Proc Int Conf Learn Represent (ICLR)"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/9466892\/09373949.pdf?arnumber=9373949","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,10]],"date-time":"2022-05-10T14:54:57Z","timestamp":1652194497000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9373949\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,7]]},"references-count":43,"journal-issue":{"issue":"7"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2021.3061508","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2021,7]]}}}