{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,18]],"date-time":"2026-03-18T13:59:37Z","timestamp":1773842377310,"version":"3.50.1"},"reference-count":44,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"8","license":[{"start":{"date-parts":[[2021,8,1]],"date-time":"2021-08-01T00:00:00Z","timestamp":1627776000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,8,1]],"date-time":"2021-08-01T00:00:00Z","timestamp":1627776000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,8,1]],"date-time":"2021-08-01T00:00:00Z","timestamp":1627776000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100012166","name":"National Key Research and Development Program of China","doi-asserted-by":"publisher","award":["2018YFB2202602"],"award-info":[{"award-number":["2018YFB2202602"]}],"id":[{"id":"10.13039\/501100012166","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"State Key Program of the National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["61934005"],"award-info":[{"award-number":["61934005"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["62074001"],"award-info":[{"award-number":["62074001"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100018537","name":"National Science and Technology Major Project","doi-asserted-by":"publisher","award":["2017ZX01028-101-003"],"award-info":[{"award-number":["2017ZX01028-101-003"]}],"id":[{"id":"10.13039\/501100018537","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"Joint Funds of the National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["U19A2074"],"award-info":[{"award-number":["U19A2074"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["61804001"],"award-info":[{"award-number":["61804001"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2021,8]]},"DOI":"10.1109\/jssc.2021.3063719","type":"journal-article","created":{"date-parts":[[2021,3,18]],"date-time":"2021-03-18T19:48:48Z","timestamp":1616096928000},"page":"2550-2562","source":"Crossref","is-referenced-by-count":47,"title":["Cascade Current Mirror to Improve Linearity and Consistency in SRAM In-Memory Computing"],"prefix":"10.1109","volume":"56","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-3314-1606","authenticated-orcid":false,"given":"Zhiting","family":"Lin","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2840-9639","authenticated-orcid":false,"given":"Honglan","family":"Zhan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zhongwei","family":"Chen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2408-5048","authenticated-orcid":false,"given":"Chunyu","family":"Peng","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5012-2570","authenticated-orcid":false,"given":"Xiulong","family":"Wu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wenjuan","family":"Lu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Qiang","family":"Zhao","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6009-7711","authenticated-orcid":false,"given":"Xuan","family":"Li","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Junning","family":"Chen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/LSSC.2019.2943874"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2963616"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2011.2165389"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2642198"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2782087"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1016\/S1369-7021(06)71539-5"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2020.3020137"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2011.5746310"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2872584"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2019.2902102"},{"key":"ref10","first-page":"490","article-title":"A 42 pJ\/decision 3.12 TOPS\/W robust in-memory machine learning classifier with on-chip training","author":"gonugondla","year":"2018","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/CICC48029.2020.9075883"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2867275"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1049\/el.2019.2415"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2019.2929245"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2018.2848999"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2018.8310397"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2019.8662435"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2018.8510687"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2019.8662392"},{"key":"ref19","first-page":"2553","article-title":"A 32 kb 9T SRAM with PVT-tracking read margin enhancement for ultra-low voltage operation","author":"do","year":"2015","journal-title":"Proc IEEE Int Symp Circuits Syst (ISCAS)"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2020.2976099"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TBCAS.2016.2545402"},{"key":"ref27","first-page":"232","article-title":"A 14 nm FinFET 128 Mb 6T SRAM with VMIN-enhancement techniques for low-power applications","author":"song","year":"2014","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2015.7169194"},{"key":"ref6","first-page":"21","article-title":"Parallelizing SRAM arrays with customized bit-cell for binary neural networks","author":"liu","year":"2018","journal-title":"Proc 55th Annu Design Autom Conf"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2003.1250885"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2018.8310401"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ICASSP.2014.6855225"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ASSCC.2016.7844125"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2018.8502421"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2009.2024663"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ICASSP.2015.7178127"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.870763"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2014.2384007"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2014.2360760"},{"key":"ref42","first-page":"242","article-title":"A 351 TOPS\/W and 372.4 GOPS compute-in-memory SRAM macro in 7 nm FinFET CMOS for machine-learning applications","author":"dong","year":"2020","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/MCD.2005.1578583"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/A-SSCC47793.2019.9056926"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2013.2291064"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2498302"},{"key":"ref26","first-page":"158","article-title":"A 45 nm 0.6 V cross-point 8T SRAM with negative biased read\/write assist","author":"yabuuchi","year":"2009","journal-title":"Proc Symp VLSI Circuits"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2019.2928043"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TBCAS.2014.2377754"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/9493684\/09381242.pdf?arnumber=9381242","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,10]],"date-time":"2022-05-10T14:54:51Z","timestamp":1652194491000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9381242\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,8]]},"references-count":44,"journal-issue":{"issue":"8"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2021.3063719","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2021,8]]}}}