{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,27]],"date-time":"2025-06-27T14:44:38Z","timestamp":1751035478101,"version":"3.37.3"},"reference-count":41,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"11","license":[{"start":{"date-parts":[[2021,11,1]],"date-time":"2021-11-01T00:00:00Z","timestamp":1635724800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,11,1]],"date-time":"2021-11-01T00:00:00Z","timestamp":1635724800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,11,1]],"date-time":"2021-11-01T00:00:00Z","timestamp":1635724800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100001381","name":"Singapore National Research Foundation","doi-asserted-by":"publisher","award":["NRF-CRP20-2017-0003"],"award-info":[{"award-number":["NRF-CRP20-2017-0003"]}],"id":[{"id":"10.13039\/501100001381","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2021,11]]},"DOI":"10.1109\/jssc.2021.3095343","type":"journal-article","created":{"date-parts":[[2021,7,21]],"date-time":"2021-07-21T20:31:48Z","timestamp":1626899508000},"page":"3533-3543","source":"Crossref","is-referenced-by-count":3,"title":["On-Chip Links With Energy-Quality Tradeoff in Error-Resilient and Machine Learning Applications"],"prefix":"10.1109","volume":"56","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-5353-7109","authenticated-orcid":false,"given":"Viveka","family":"Konandur Rajanna","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4127-8258","authenticated-orcid":false,"given":"Massimo","family":"Alioto","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2881913"},{"key":"ref38","first-page":"238","article-title":"A 2.9TOPS\/W deep convolutional neural network SoC in FD-SOI 28 nm for intelligent embedded systems","author":"desoli","year":"2017","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/5.726791"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2019.8780323"},{"key":"ref31","article-title":"Deep compression: Compressing deep neural networks with pruning, trained quantization and Huffman coding","author":"han","year":"2015","journal-title":"arXiv 1510 00149 [cs]"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1145\/3145812"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/4.826812"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2900866"},{"key":"ref35","first-page":"182","article-title":"High-bandwidth and low-energy on-chip signaling with adaptive pre-emphasis in 90 nm CMOS","author":"seo","year":"2010","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref34","first-page":"1","article-title":"ImageNet classification with deep convolutional neural networks","author":"krizhevsky","year":"2012","journal-title":"Proc Adv Neural Inf Process Syst"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2018.2881461"},{"journal-title":"The MNIST Database of Handwritten Digits","year":"2020","author":"lecun","key":"ref40"},{"key":"ref11","first-page":"242","article-title":"14.3 A 28 nm SoC with a 1.2 GHz 568nJ\/prediction sparse deep-neural-network engine with >0.1 timing error rate tolerance for IoT applications","author":"whatmough","year":"2017","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/3195970.3195997"},{"key":"ref13","article-title":"Parallel architectures and bioinspired algorithms","author":"de vega","year":"2012","journal-title":"Studies in Computational Intelligence"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2820145"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2408332"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2016.7573525"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2020.2968576"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2017.7870350"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2018.8310262"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.847907"},{"key":"ref4","first-page":"400","article-title":"A 0.1 pJ\/b 5-to-10Gb\/s charge-recycling stacked low-power I\/O for on-chip signaling in 45 nm CMOS SOI","author":"liu","year":"2013","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref27","first-page":"262","article-title":"A 95fJ\/b current-mode transceiver for 10 mm on-chip interconnect","author":"lee","year":"2013","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2018.8357077"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2011.6055384"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080241"},{"key":"ref5","doi-asserted-by":"crossref","first-page":"1637","DOI":"10.7873\/DATE.2013.332","article-title":"40.4 FJ\/bit\/mm low-swing on-chip signaling with self-resetting logic repeaters embedded within a mesh NoC in 45 nm SOI CMOS","author":"park","year":"2013","journal-title":"Proc Design Automat Eur Conf Exhib"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2369508"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2352303"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-51482-6"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC19947.2020.9063126"},{"key":"ref1","first-page":"156","article-title":"8.6 A 6.5-to-23.3 fJ\/b\/mm balanced charge-recycling bus in 16 nm FinFET CMOS at 1.7-to-2.6 Gb\/s\/wire with clock forwarding and low-crosstalk contraflow wiring","author":"wilson","year":"2016","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2358589"},{"article-title":"Self-calibrating on-chip interconnects","year":"2012","author":"chen","key":"ref22"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2011.5746277"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/92.845893"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2009.5206848"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2004.834241"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2013.080"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2036761"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/9583614\/09492044.pdf?arnumber=9492044","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T19:54:17Z","timestamp":1725479657000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9492044\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,11]]},"references-count":41,"journal-issue":{"issue":"11"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2021.3095343","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"type":"print","value":"0018-9200"},{"type":"electronic","value":"1558-173X"}],"subject":[],"published":{"date-parts":[[2021,11]]}}}